Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
198
21.5 Functional Description
21.5.1 SDRAM Controller Write Cycle
The SDRAM Controller allows burst access or single access. In both cases, the SDRAM controller keeps track of
the active row in each bank, thus maximizing performance. To initiate a burst access, the SDRAM Controller uses
the transfer type signal provided by the master requesting the access. If the next access is a sequential write
access, writing to the SDRAM device is carried out. If the next access is a write-sequential access, but the current
access is to a boundary page, or if the next access is in another row, then the SDRAM Controller generates a
precharge command, activates the new row and initiates a write command. To comply with SDRAM timing
parameters, additional clock cycles are inserted between precharge/active (t
RP
) commands and active/write (t
RCD
)
commands. For definition of these timing parameters, refer to the “SDRAMC Configuration Register” on page 208.
This is described in Figure 21-2 below.
Figure 21-2. Write Burst, 32-bit SDRAM Access
SDCK
SDCS
RAS
CAS
SDRAMC_A[12:0]
D[31:0]
t
RCD
= 3
Dna
SDWE
Dnb Dnc Dnd
Dne
Dnf
Dng Dnh
Dni Dnj
Dnk Dnl
Row n col a col b col c col d col e col f col g col h col i col j col k col l