Datasheet

197

SAM9261 [DATASHEET]

Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16

Figure 21-1. SDRAM Device Initialization Sequence

21.4.2 I/O Lines

The pins used for interfacing the SDRAM Controller may be multiplexed with the PIO lines. The programmer must

first program the PIO controller to assign the SDRAM Controller pins to their peripheral function. If I/O lines of the

SDRAM Controller are not used by the application, they can be used for other purposes by the PIO Controller.

21.4.3 Interrupt

The SDRAM Controller interrupt (Refresh Error notification) is connected to the Memory Controller. This interrupt

may be ORed with other System Peripheral interrupt lines and is finally provided as the System Interrupt Source

(Source 1) to the AIC (Advanced Interrupt Controller).

Using the SDRAM Controller interrupt requires the AIC to be programmed first.

SDCK

SDRAMC_A[9:0]

A10

SDRAMC_A[12:11]

SDCS

RAS

CAS

SDWE

NBS

Inputs Stable for

200 μsec

Precharge All Banks 1st Auto-refresh 8th Auto-refresh MRS Command Valid Command

SDCKE

MRD