Datasheet

193
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
21. SDRAM Controller (SDRAMC)
21.1 Overview
The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to an
external 16-bit or 32-bit SDRAM device. The page size supports ranges from 2048 to 8192 and the number of
columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses.
The SDRAM Controller supports a read or write burst length of one location. It keeps track of the active row in each
bank, thus maximizing SDRAM performance, e.g., the application may be placed in one bank and data in the other
banks. So as to optimize performance, it is advisable to avoid accessing different rows in the same bank.
The SDRAM controller supports a CAS latency of 1, 2 or 3 and optimizes the read access depending on the
frequency.
The different modes available - self-refresh, powerdown and deep powerdown modes - minimize power
consumption on the SDRAM device.
21.2 I/O Lines Description
Table 21-1. I/O Line Description
Name Description Type Active Level
SDCK SDRAM Clock Output
SDCKE SDRAM Clock Enable Output High
SDCS SDRAM Controller Chip Select Output Low
BA[1:0] Bank Select Signals Output
RAS Row Signal Output Low
CAS Column Signal Output Low
SDWE SDRAM Write Enable Output Low
NBS[3:0] Data Mask Enable Signals Output Low
SDRAMC_A[12:0] Address Bus Output
D[31:0] Data Bus I/O