Datasheet

19
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
Note: 1. EBI NCS0 is to be connected to a 16-bit non-volatile memory. The access configuration is defined by the reset state of SMC
Setup, SMC Pulse, SMC Cycle and SMC Mode CS0 registers.
7.1.1.1 Internal SRAM
The SAM9261 embeds a high-speed 160 Kbyte SRAM. This Internal SRAM is split into three areas. Its Memory
Mapping is detailed in Table 7-3 above.
 Internal SRAM A is the ARM926EJ-S Instruction TCM and the user can map this SRAM block anywhere in
the ARM926 instruction memory space using CP15 instructions. This SRAM block is also accessible by the
ARM926 Data Master and by the AHB Masters through the AHB bus at address 0x0010 0000.
 Internal SRAM B is the ARM926EJ-S Data TCM and the user can map this SRAM block anywhere in the
ARM926 data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926
Data Master and by the AHB Masters through the AHB bus at address 0x0020 0000.
 Internal SRAM C is only accessible by all the AHB Masters.
After reset and until the Remap Command is performed, this SRAM block is accessible through the AHB bus
at address 0x0030 0000 by all the AHB Masters.
After Remap, this SRAM block also becomes accessible through the AHB bus at address 0x0 by the
ARM926 Instruction and the ARM926 Data Masters.
Within the 160 Kbyte SRAM size available, the amount of memory assigned to each block is software
programmable as a multiple of 16 Kbytes according to Table 7-4. This table provides the size of the Internal SRAM
C according to the size of the Internal SRAM A and the Internal SRAM B.
Note that among the ten 16 Kbyte blocks making up the Internal SRAM, two are permanently assigned to Internal
SRAM C.
At reset, the whole memory (160 Kbytes) is assigned to Internal SRAM C.
The memory blocks assigned to SRAM A, SRAM B and SRAM C areas are not contiguous and when the user
dynamically changes the Internal SRAM configuration, the new 16 Kbyte block organization may affect the
previous configuration from a software point of view.
Table 7-5 illustrates different configurations and the related 16 Kbyte blocks (RB0 to RB9) assignments.
Table 7-3. Internal Memory Mapping
Address
Master 0: ARM926 Instruction Master 1: ARM926 Data
REMAP (RCB0) = 0
REMAP (RCB0) = 1
REMAP (RCB1) = 0
REMAP (RCB1) = 1BMS = 1 BMS = 0 BMS = 1 BMS = 0
0x0000 0000 Internal ROM EBI NCS0
(1)
Internal RAM C Internal ROM EBI NCS0
(1)
Internal RAM C
Table 7-4. Internal SRAM Block Size
Internal SRAM C
Internal SRAM A (ITCM)
0 16 Kbytes 32 Kbytes 64 Kbytes
Internal SRAM B (DCTM)
0
160 Kbytes 144 Kbytes 128 Kbytes 96 Kbytes
16 Kbytes
144 Kbytes 128 Kbytes 112 Kbytes 80 Kbytes
32 Kbytes
128 Kbytes 112 Kbytes 96 Kbytes 64 Kbytes
64 Kbytes
96 Kbytes 80 Kbytes 64 Kbytes 32 Kbytes