Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
164
Figure 20-12. Write Cycle
20.8.3.3 Write Cycle
The write cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on
the address bus to the point where address may change. The total write cycle time is equal to:
NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD,
as well as
NWE_CYCLE= NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD
All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock
cycles. The NWE_CYCLE field is common to both the NWE and NCS signals, thus the timing period is of the same
duration.
NWE_CYCLE, NWE_SETUP, and NWE_PULSE implicitly define the NWE_HOLD value as:
NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE
NWE_CYCLE, NCS_WR_SETUP, and NCS_WR_PULSE implicitly define the NCS_WR_HOLD value as:
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE
A
[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NCS
NWE_SETUP NWE_PULSE NWE_HOLD
MCK
NWE
NCS_WR_SETUP
NCS_WR_PULSE
NCS_WR_HOLD
NWE_CYCLE