Datasheet

133
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
19.3 I/O Lines Description
The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use
at the moment.
Table 19-2 on page 134 details the connections between the two Memory Controllers and the EBI pins.
Table 19-1. I/O Lines Description
Name Function Type Active Level
EBI
D0–D31 Data Bus I/O
A0–A25 Address Bus Output
NWAIT External Wait Signal Input Low
SMC
NCS0–NCS7 Chip Select Lines Output Low
NWR0–NWR3 Write Signals Output Low
NRD Read Signal Output Low
NWE Write Enable Output Low
NBS0–NBS3 Byte Mask Signals Output Low
EBI for CompactFlash Support
CFCE1–CFCE2 CompactFlash Chip Enable Output Low
CFOE CompactFlash Output Enable Output Low
CFWE CompactFlash Write Enable Output Low
CFIOR CompactFlash I/O Read Signal Output Low
CFIOW CompactFlash I/O Write Signal Output Low
CFRNW CompactFlash Read Not Write Signal Output
CFCS0–CFCS1 CompactFlash Chip Select Lines Output Low
EBI for NAND Flash Support
NANDCS NAND Flash Chip Select Line Output Low
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
SDRAM Controller
SDCK SDRAM Clock Output
SDCKE SDRAM Clock Enable Output High
SDCS SDRAM Controller Chip Select Line Output Low
BA0–BA1 Bank Select Output
SDWE SDRAM Write Enable Output Low
RAS - CAS Row and Column Signal Output Low
NWR0–NWR3 Write Signals Output Low
NBS0–NBS3 Byte Mask Signals Output Low
SDA10 SDRAM Address 10 Line Output