Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
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18.4 Arbitration
The Bus Matrix provides an arbitration function that reduces latency when conflicting cases occur, i.e., when two or
more masters try to access the same slave at the same time. The Bus Matrix arbitration mechanism uses slightly
modified round-robin algorithms that grant the bus for the first access to a certain master depending on parameters
located in the slave’s Slave Configuration Register.
There are three round-robin algorithm types:
 Round-Robin arbitration without default master
 Round-Robin arbitration with last access master
 Round-Robin arbitration with fixed default master
18.4.1 Round-Robin Arbitration Without Default Master
This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch requests from different
masters to the same slave in a pure round-robin manner. At the end of the current access, if no other request is
pending, the slave is disconnected from all masters. This configuration incurs one latency cycle for the first access.
Arbitration without default master can be used for masters that perform significant bursts.
18.4.2 Round-Robin Arbitration With Last Access Master
This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove one latency
cycle for the last master that accessed the slave. In fact, at the end of the current transfer, if no other master
request is pending, the slave remains connected to the last master that performs the access. Other non-privileged
masters still obtain one latency cycle if they want to access the same slave. This technique can be used for
masters that perform mainly single accesses.
18.4.3 Round-Robin Arbitration With Fixed Default Master
This is a biased round-robin algorithm. It allows the Bus Matrix arbiters to remove one latency cycle for the fixed
master of a slave. At the end of the current access, the slave remains connected to its fixed default master. Any
request attempted by this fixed default master does not cause any latency, whereas other non-privileged masters
still obtain one latency cycle. This technique can be used for masters that perform mainly single accesses.