Datasheet

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SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
18. Bus Matrix
18.1 Overview
The Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel access paths
between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix
interconnects 5 AHB Masters to 5 AHB Slaves. The Bus Matrix user interface is compliant with the ARM Advanced
Peripheral Bus and provides 5 Special Function Registers (MATRIX_SFR) that allow the Bus Matrix to support
application-specific features.
18.2 Memory Mapping
The Bus Matrix provides one decoder for every AHB Master Interface. The decoder offers each AHB Master
several memory mappings. Depending on the product, each memory area may be assigned to several slaves.
Booting at the same address while using different AHB slaves (i.e., external RAM, internal ROM, internal Flash,
etc.) becomes possible.
The Bus Matrix user interface provides a Master Configuration Register (MATRIX_MCFG) that performs a remap
action for every master independently.
18.3 Special Bus Granting Techniques
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from
some masters. This technique reduces latency at first accesses. The bus granting technique sets a default master
for every slave. At the end of the current access, if no other request is pending, the slave remains connected to its
associated default master. A slave can be associated with three kinds of default masters; no default master, last
access master and fixed default master.
18.3.1 No Default Master
At the end of current access, if no other request is pending, the slave is disconnected from all masters. No Default
Master suits low-power mode.
18.3.2 Last Access Master
At the end of current access, if no other request is pending, the slave remains connected to the last master that
performs an access request.
18.3.3 Fixed Default Master
At the end of current access, if no other request is pending, the slave remains connected to its fixed default
master. Unlike last access master, the fixed master does not change unless the user changes it by a software
action.
To change from one kind of default master to another, the Bus Matrix user interface provides 5 Slave Configuration
Registers, one for each slave, that set default master for each slave. The Slave Configuration Register contains
two fields; DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE flag selects the default master
type (no default, last access master, fixed default master) whereas the 3-bit FIXED_DEFMSTR flag selects a fixed
default master provided that DEFMSTR_TYPE is set to a fixed default master. See Section 18.5 “Bus Matrix
(MATRIX) User Interface”.