Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
12
4.2.1 Powerup Sequence
Figure 4-1. VDDCORE and VDDIO Constraints at Startup
VDDCORE and VDDBU are controlled by internal POR (Power-On-Reset) to guarantee that these power sources
reach their target values prior to the release of POR.
 VDDIOP must be ≥ to VIH (refer to Table 38-2 “DC Characteristics” for more details) within (t
RST
+ T1) after
VDDCORE has reached V
T+
.
 VDDIOM must reach VOH (refer to Table 38-2 “DC Characteristics” for more details) within (t
RST
+ T1 + T2)
after VDDCORE has reached V
T+
.
 t
RST
is a POR characteristic
 T1 = 3 x t
SLCK
 T2 = 16 x t
SLCK
As t
SLCK
is the period of the external 32.768 kHz oscillator.
 t
RST
= 50 µs
 T1 = 91.5 µs
 T2 = 488 µs
4.2.2 Powerdown Sequence
Switch off the VDDIOM and VDDIOP power supply prior to or at the same time as VDDCORE. No powerup or
powerdown restrictions apply to other power supplies.
VDD (V)
Core Supply POR Output
VDDIOtyp
Vih
V
T+
t
SLCK
<--- t
RST
--->
VDDIO > Vih
VDDCORE
VDDIO
< T1 >
VDDCOREtyp
Voh
VDDIO > Voh
<------------ T2----------->