Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
108
15. Periodic Interval Timer (PIT)
15.1 Overview
The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer
maximum accuracy and efficient management, even for systems with long response time.
15.2 Embedded Characteristics
 Includes a 20-bit Periodic Counter with less than 1 µs accuracy
 Includes a 12-bit Interval Overlay Counter
 Real time OS or Linux
®
/WindowsCE
®
compliant tick generator
15.3 Block Diagram
Figure 15-1. Periodic Interval Timer
15.4 Functional Description
The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems.
The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a
20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16.
The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the
Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic
Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt,
provided the interrupt is enabled (PITIEN in PIT_MR).
Writing a new PIV value in PIT_MR does not reset/restart the counters.
20-bit
Counter
MCK/16
PIV
PIT_MR
CPIV
PIT_PIVR
PICNT
12-bit
Adder
0
0
read PIT_PIVR
CPIV PICNT
PIT_PIIR
PITS
PIT_SR
set
reset
PITIEN
PIT_MR
pit_irq
1
0
10
MCK
Prescaler
= ?