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Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16

Description

The Atmel

| SMART SAM9261 is a complete system-on-chip built around the

ARM926EJ-S™ ARM

Thumb

processor with an extended DSP instruction set

and Jazelle

Java

accelerator. It achieves 210 MIPS at 190 MHz.

The SAM9261 is an optimized host processor for applications with an LCD

display. Its integrated LCD controller supports BW and up to 16M color, active and

passive LCD displays. The 160 Kbyte integrated SRAM can be configured as a

frame buffer minimizing the impact for LCD refresh on the overall processor

performance. The External Bus Interface incorporates controllers for synchronous

DRAM (SDRAM) and Static memories and features specific interface circuitry for

CompactFlash and NAND Flash.

The SAM9261 integrates a ROM-based bootloader supporting code shadowing

from, for example, external DataFlash

into external SDRAM. The software

controlled Power Management Controller (PMC) keeps system power

consumption to a minimum by selectively enabling/disabling the processor and

various peripherals and adjustment of the operating frequency.

The SAM9261 also benefits from the integration of a wide range of debug features

including JTAG-ICE, a dedicated UART debug channel (DBGU) and an

embedded real time trace. This enables the development and debug of all

applications, especially those with real-time constraints.

SAM9261

Atmel | SMART ARM-based Embedded MPU

DATASHEET

Summary of content (749 pages)

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SAM9261 Atmel | SMART ARM-based Embedded MPU DATASHEET Description The Atmel® | SMART SAM9261 is a complete system-on-chip built around the ARM926EJ-S™ ARM® Thumb® processor with an extended DSP instruction set and Jazelle® Java® accelerator. It achieves 210 MIPS at 190 MHz. The SAM9261 is an optimized host processor for applications with an LCD display. Its integrated LCD controller supports BW and up to 16M color, active and passive LCD displays.
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Features 2  ARM926EJ-S ARM ThumbProcessor ̶ DSP Instruction Extensions ̶ ARM Jazelle Technology for Java Acceleration ̶ 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer ̶ 210 MIPS at 190 MHz ̶ Memory Management Unit ̶ EmbeddedICE™, Debug Communication Channel Support ̶ Mid-level implementation Embedded Trace Macrocell® (ETM®)  Additional Embedded Memories ̶ 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed ̶ 160 Kbytes of Internal SRAM, Single-cycle Access at Maximum Pr
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 Debug Unit (DBGU) ̶ 2-wire USART and support for Debug Communication Channel, Programmable ICE Access Prevention ̶ Mode for General Purpose Two-wire UART Serial Communication  Periodic Interval Timer (PIT) ̶ 20-bit Interval Timer plus 12-bit Interval Counter  Watchdog Timer (WDT) ̶ Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running at Slow Clock  Real-Time Timer (RTT) ̶ 32-bit Free-running Backup Counter Running at Slow Clock  Three 32-bit Parallel Input/Output Controller
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Block Diagram ARM926EJ-S Core ICE Instruction Cache 16 Kbytes TCM Interface System Controller PLLRCA PLLA PLLB 5-layer Matrix RTT VDDCORE POR Peripheral Bridge Backup Section POR SDRAM Controller PIT SHDWC VDDBU GNDBU EBI CompactFlash NAND Flash Fast ROM 32 Kbytes GPBR (16 bytes) SHDN WKUP D DTCM 3–20 MHz Main Osc. 32 kHz XTAL Osc.
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2. Signal Description Table 2-1. Signal Name Signal Description by Peripheral Function Type Active Level Comments Power VDDIOM EBI I/O Lines Power Supply Power 1.65–1.95 V and 3.0–3.6 V VDDIOP Peripherals I/O Lines Power Supply Power 2.7–3.6 V VDDBU Backup I/O Lines Power Supply Power 1.08–1.32 V VDDPLL PLL Power Supply Power 3.0–3.6 V VDDOSC Oscillator Power Supply Power 3.0–3.6 V VDDCORE Core Chip Power Supply Power 1.08–1.
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Table 2-1.
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Table 2-1.
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Table 2-1.
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3. Package and Pinout 3.1 217-ball LFBGA Package Outline Figure 3-1 shows the orientation of the 217-ball LFBGA package. A detailed mechanical description is given in Section 39. “Mechanical Characteristics”. Figure 3-1. 217-ball LFBGA Package Outline (Top View) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U Ball A1 3.2 Pinout Table 3-1.
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Table 3-1.
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4. Power Considerations 4.1 Power Supplies The SAM9261 device has several types of power supply pins. Some supply pins share common ground (GND) pins whereas others have separate grounds. See Table 4-1. Table 4-1. SAM9263 Power Supply Pins Pin(s) Item(s) powered VDDCORE Core, including the processor Embedded memories Peripherals VDDIOM External Bus Interface I/O lines Range Nominal 1.08–1.32 V 1.2V 1.65–1.95 V(1) 1.8V 3.0–3.6 V (1) Ground GND 3.
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4.2.1 Powerup Sequence Figure 4-1. VDDCORE and VDDIO Constraints at Startup VDD (V) VDDIO VDDIOtyp VDDIO > Voh Voh VDDIO > Vih Vih VDDCORE VDDCOREtyp VT+ t <--- tRST ---> < T1 > <------------ T2-----------> Core Supply POR Output SLCK VDDCORE and VDDBU are controlled by internal POR (Power-On-Reset) to guarantee that these power sources reach their target values prior to the release of POR.
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5. I/O Line Considerations 5.1 JTAG Port Pins TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP, and have no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied to VDDBU). It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations.
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6. Processor and Architecture 6.
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6.2 Debug and Test Features     6.
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6.4 16 Peripheral DMA Controller  Transfers from/to peripheral to/from any memory space without intervention of the processor.  Next Pointer Support, forbids strong real-time constraints on buffer management.
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7. Memories Figure 7-1.
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A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 areas of 256 Mbytes. The areas 1 to 8 are directed to the EBI that associates these areas to the external chip selects NCS0 to NCS7.
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Table 7-3. Internal Memory Mapping Master 0: ARM926 Instruction REMAP (RCB0) = 0 Master 1: ARM926 Data REMAP (RCB1) = 0 Address BMS = 1 BMS = 0 REMAP (RCB0) = 1 BMS = 1 BMS = 0 REMAP (RCB1) = 1 0x0000 0000 Internal ROM EBI NCS0(1) Internal RAM C Internal ROM EBI NCS0(1) Internal RAM C Note: 1. EBI NCS0 is to be connected to a 16-bit non-volatile memory. The access configuration is defined by the reset state of SMC Setup, SMC Pulse, SMC Cycle and SMC Mode CS0 registers. 7.1.1.
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Table 7-5.
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When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware at reset. Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the complete memory map presented in Figure 7-1 on page 17. The SAM9261 Bus Matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose.
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Table 7-6. 7.
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8. System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Peripherals are all mapped within the highest 6 Kbytes of address space, between addresses 0xFFFF EA00 and 0xFFFF FFFF. Each peripheral has an address space of 256 or 512 bytes, representing 64 or 128 registers. Figure 8-1 on page 24 shows the System Controller block diagram.
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8.1 Block Diagram Figure 8-1. System Controller Block Diagram System Controller irq0–irq2 fiq nirq nfiq Advanced Interrupt Controller periph_irq[2..
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8.2 Reset Controller See Section 13.2 “Embedded Characteristics”. 8.3 Shutdown Controller See Section 16.2 “Embedded Characteristics”. 8.4 General-purpose Backup Registers  8.5 Four 32-bit general-purpose backup registers Clock Generator  Embeds the Low-power 32.
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8.6 Power Management Controller  The Power Management Controller provides: ̶ the Processor Clock PCK ̶ the Master Clock MCK ̶ the USB Clock USBCK (HCK0) ̶ the LCD Controller Clock LCDCK (HCK1) ̶ up to thirty peripheral clocks ̶ four programmable clock outputs: PCK0 to PCK3 Figure 8-3. Power Management Controller Block Diagram Processor Clock Controller int Master Clock Controller SLCK MAINCK PLLACK PLLBCK PCK Idle Mode Divider /1,/2,/4 Prescaler /1,/2,/4,...
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8.10 Advanced Interrupt Controller  Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor  Thirty-two individually maskable and vectored interrupt sources ̶ ̶ Source 0 is reserved for the Fast Interrupt Input (FIQ) Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.
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9. Peripherals 9.1 User Interface The User Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 7-1 on page 17. 9.2 Peripheral Identifiers Table 9-1 defines the Peripheral Identifiers of the SAM9261.
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9.3 Peripheral Multiplexing on PIO Lines The SAM9261 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two peripheral functions, A or B. The tables in Section 9.3.2 “PIO Controller Multiplexing Tables” define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers.
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9.3.1.6 CompactFlash Interface Using the CompactFlash interface prevents:  using NCS4 and/or NCS5 to access other parallel devices 9.3.1.7 SPI0 and the MultiMedia Card Interface As the DataFlash Card is compatible with the SDCard, it is useful to multiplex SPI and MCI. Here, the SPI0 signal is multiplexed with the MCI. 9.3.1.8 USARTs  Using the USART1 and USART2 control signals prevents using the ETM.
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9.3.2 PIO Controller Multiplexing Tables Table 9-2.
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Table 9-3.
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Table 9-4.
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9.3.3 System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:  the SDRAM Controller  the Debug Unit  the Periodic Interval Timer  the Real-Time Timer  the Watchdog Timer  the Reset Controller  the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 9.3.4 External Interrupts All external interrupt signals, i.e.
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9.5 Static Memory Controller  External memory mapping, 256 Mbyte address space per Chip Select Line  Up to Eight Chip Select Lines  8, 16 or 32-bit Data Bus  Multiple Access Modes supported    9.
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9.7 Serial Peripheral Interface    9.
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9.10 9.11 Synchronous Serial Controller  Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader and more).  Contains an independent receiver and transmitter and a common clock divider.  Offers a configurable frame sync and data length.  Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal.
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10. ARM926EJ-S Processor 10.1 Overview The ARM926EJ-S processor is a member of the ARM9™ family of general-purpose microprocessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi-tasking applications where full memory management, high performance, low die size and low power are all important features. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off between high performance and high code density.
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10.2 Block Diagram Figure 10-1. ARM926EJ-S Internal Functional Block Diagram ARM926EJ-S TCM Interface Coprocessor Interface ETM Interface DEXT Droute Data AHB Interface AHB DCACHE WDATA Bus Interface Unit RDATA ARM9EJ-S DA MMU EmbeddedICE -RT Processor Instruction AHB Interface IA AHB INSTR ICE Interface ICACHE Iroute IEXT 10.3 ARM9EJ-S Processor 10.3.
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All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or Jazelle states, the processor reverts to ARM state. The transition back to Thumb or Jazelle states occurs automatically on return from the exception handler. 10.3.3 Instruction Pipelines The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. A five-stage (five clock cycles) pipeline is used for ARM and Thumb states.
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10.3.7 ARM9EJ-S Registers The ARM9EJ-S core has a total of 37 registers.  31 general-purpose 32-bit registers  Six 32-bit status registers Table 10-1 shows all the registers in all modes. Table 10-1.
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In all modes and due to a software agreement, register r13 is used as stack pointer. The use and the function of all the registers described above should obey ARM Procedure Call Standard (APCS) which defines:  constraints on the use of registers  stack conventions  argument passing and result return The Thumb state register set is a subset of the ARM state set.
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10.3.7.2 Exceptions Exception Types and Priorities The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privileged mode. The types of exceptions are:  Fast interrupt (FIQ)  Normal interrupt (IRQ)  Data and Prefetched aborts (Abort)  Undefined instruction (Undefined)  Software interrupt and Reset (Supervisor) When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state.
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The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching. The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage in the pipeline.
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Table 10-2.
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10.3.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into:  Branch instructions  Data processing instructions  Load and Store instructions  Load and Store multiple instructions  Exception-generating instruction Table 10-4 gives the Thumb instruction mnemonic list. Table 10-4.
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10.4 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below:  ARM9EJ-S  Caches (ICache, DCache and write buffer)  TCM  MMU  Other system options To control these features, CP15 provides 16 additional registers. See Table 10-5. Table 10-5. CP15 Registers Register 0 1. 2.
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10.4.1 CP15 Registers Access CP15 registers can only be accessed in privileged mode by:  MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15.  MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2.
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10.5 Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS®, Windows CE, and Linux. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13.
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10.5.3 Translation Table Walk Hardware The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB. The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. There are three sizes of page-mapped accesses and one size of section-mapped access.
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mapped to the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning and/or invalidating. When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in page 4-4 in ARM926EJ-S TRM, ref. DDI0198B). On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be enabled as soon as possible after reset. 10.6.
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Write-back Operation When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not upto-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 10.7 Tightly-Coupled Memory Interface 10.7.
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10.8.1 Supported Transfers The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. Table 10-7 gives an overview of the supported transfers and different kinds of transactions they are used for. Table 10-7.
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11. Debug and Test 11.1 Overview The SAM9261 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. An ETM (Embedded Trace Macrocell) provides more sophisticated debug features such as address and data comparators, half-rate clock mode, counters, sequencer and FIFO.
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11.3 Application Examples 11.3.1 Debug Environment Figure 11-2 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. The Trace Port interface is used for tracing information. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 11-2.
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11.4 Debug and Test Pin Description Table 11-1.
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11.5 Functional Description 11.5.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 11.5.2 Embedded In-circuit Emulator The ARM9EJ-S EmbeddedICE-RT™ is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface.
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The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The SAM9261 Debug Unit Chip ID value is 0x0197 03A0 on 32-bit width. For further details on the Debug Unit, see Section 27.
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Figure 11-4. ETM9 Block TPS-TPS0 ARM926EJ-S Bus Tracker Trace Control FIFO TPK15-TPK0 TSYNC Trace Enable, View Data TAP Controller Trigger, Sequencer, Counters Scan Chain 6 TDO TDI TMS TCK ETM9 11.5.5.2 Implementation Details This section gives an overview of the Embedded Trace resources. Three-state Sequencer The sequencer has three possible next states (one dedicated to itself and two others) and can change on every clock cycle. The state transition is controlled with internal events.
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Table 11-2.
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Figure 11-6. AMP Mictor Connector Orientation AT91SAM9261-based Application Board 38 37 2 1 Pin 1Chamfer 11.5.6 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system.
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Table 11-3.
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Table 11-3.
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Table 11-3.
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Table 11-3.
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Table 11-3.
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Table 11-3.
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Table 11-3.
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Table 11-3.
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Table 11-3.
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Table 11-3.
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Table 11-3.
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Table 11-3.
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Table 11-3.
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11.5.7 ID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 3 2 1 MANUFACTURER IDENTITY 0 1 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B08 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B0_803F.
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12. Boot Program 12.1 Description The boot program integrates different programs that manage download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB High Speed Device Port. The boot program tries to detect SPI flash memories. The Serial Flash boot program and DataFlash boot program are executed. It looks for a sequence of seven valid ARM exception vectors in a Serial Flash or DataFlash connected to the SPI.
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12.2 Flow Diagram The Boot Program implements the algorithm in Figure 12-1. Figure 12-1.
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12.3 Device Initialization Initialization follows the steps described below: 1. Stack setup for ARM supervisor mode 2. Main Oscillator Frequency Detection 3. C variable initialization 4. PLL setup: PLLB is initialized to generate a 48 MHz clock necessary to use the USB Device. A register located in the Power Management Controller (PMC) determines the frequency of the main oscillator and thus the correct factor for the PLLB. Table 12-1 defines the crystals supported by the boot program. Table 12-1.
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12.4 Valid Image Detection The boot software looks for a valid application by analyzing the first 28 bytes corresponding to the ARM exception vectors. These bytes must implement ARM instructions for either branch or load PC with PC relative addressing. The sixth vector, at offset 0x14, contains the size of the image to download. The user must replace this vector with his own vector (see Section 12.4.2 “Structure of ARM Vector 6”). 12.4.1 Valid ARM Exception Vectors Figure 12-3.
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12.5 Serial Flash Boot The Serial Flash boot looks for a valid application in the SPI Serial Flash memory. SPI0 is configured in mater mode to generate a SPCK at 8 MHz. Serial Flash shall be connected to NPCS0. The Serial Flash boot reads the serial flash status register (Instruction code 0x05). The serial flash is considered as ready if bit 0 of the returned status register is cleared. If no serial flash is connected or if it does not answer, Serial Flash boots exits after a 1000 attempts.
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12.6 DataFlash Boot Sequence The DataFlash boot looks for a valid application in the SPI DataFlash memory. SPI0 is configured in mater mode to generate a SPCK at 8 MHz. Serial Flash shall be connected to NPCS0. The DataFlash boot reads the DataFlash flash status register (Instruction code 0xD7). The DataFlash is considered as ready if bit 7 of the returned status register is set. If no DataFlash is connected or if it does not answer, DataFlash boot exits after 1000 attempts.
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12.7 NAND Flash Boot The NAND Flash Boot program searches for a valid application in the NAND Flash memory. The first block must be guaranteed by the manufacturer. There is no ECC check. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. See “Valid Image Detection” on page 79 for more information on Valid Image Detection. 12.7.1 Supported NAND Flash Devices Any 8 or 16-bit NAND Flash devices. 12.
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12.10 SAM-BA Boot If no valid DataFlash device has been found during the DataFlash boot sequence, the SAM-BA boot program is performed. The SAM-BA boot principle is to: ̶ Wait for USB Device enumeration. ̶ In parallel, wait for character(s) received on the DBGU ̶ Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as in Table 12-2. Table 12-2.
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12.10.1 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work.
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The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document USB Basic Application, literature number 6123, for more details. 12.10.3.
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The SPI and NAND Flash drivers use several PIOs in alternate functions to communicate with devices. Care must be taken when these PIOs are used by the application. The devices connected could be unintentionally driven at boot time, and electrical conflicts between SPI output pins and the connected devices may appear. To assure correct functionality, it is recommended to plug in critical devices to other pins. Table 12-5 contains a list of pins that are driven during the boot program execution.
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13. Reset Controller (RSTC) 13.1 Overview The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 13.2 Embedded Characteristics  Based on two Power-on-Reset cells  Status of the last reset ̶  13.
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13.4 Functional Description 13.4.1 Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals:  proc_nreset: Processor reset line. It also resets the Watchdog Timer.  backup_nreset: Affects all the peripherals powered by VDDBU.  periph_nreset: Affects the whole set of embedded peripherals.  nrst_out: Drives the NRST pin.
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13.4.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
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13.4.4 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 13.4.4.1 General Reset A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises and is filtered with a Startup Counter, which operates at Slow Clock.
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13.4.4.2 Wakeup Reset The Wakeup Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during 2 Slow Clock cycles, depending on the requirements of the ARM processor. At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to report a Wakeup Reset.
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13.4.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 2-cycle processor startup.
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13.4.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1:  PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.  PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.
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13.4.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 2 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:  If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state.
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13.4.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order:  Backup Reset  Wakeup Reset  Watchdog Reset  Software Reset  User Reset Particular cases are listed below:  When in User Reset: ̶ ̶ A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal.   A software reset is impossible, since the processor reset is being activated.
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13.4.6 Reset Controller Status Register The Reset Controller Status Register (RSTC_SR) provides several status fields:  RSTTYP field: This field gives the type of the last reset, as explained in previous sections.  SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.
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13.5 Reset Controller (RSTC) User Interface Table 13-1. Register Mapping Offset Register Name 0x00 Control Register (1) Access Reset RSTC_CR Write-only - Backup Reset 0x04 Status Register RSTC_SR Read-only 0x0000_0001 0x0000_0000 0x08 Mode Register RSTC_MR Read/Write - 0x0000_0000 Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wakeup Reset depending on last rising power supply.
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13.5.1 Reset Controller Control Register Name: RSTC_CR Address: 0xFFFFFD00 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0: No effect. 1: If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0: No effect. 1: If KEY is correct, resets the peripherals. • EXTRST: External Reset 0: No effect.
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13.5.2 Reset Controller Status Register Name: RSTC_SR Address: 0xFFFFFD04 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS • URSTS: User Reset Status 0: No high-to-low edge on NRST happened since the last read of RSTC_SR. 1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
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13.5.3 Reset Controller Mode Register Name: RSTC_MR Address: 0xFFFFFD08 Access: Read/Write 31 30 29 28 27 26 25 24 17 – 16 9 8 1 – 0 URSTEN KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 URSTIEN 3 – ERSTL 2 – • URSTEN: User Reset Enable 0: The detection of a low level on the pin NRST does not generate a User Reset. 1: The detection of a low level on the pin NRST triggers a User Reset.
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14. Real-time Timer (RTT) 14.1 Overview The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt and/or triggers an alarm on a programmed value. 14.2 14.3 Embedded Characteristics  32-bit Free-running backup counter  Alarm Register capable to generate a wakeup of the system Block Diagram Figure 14-1.
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executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value.
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14.5 Real-time Timer (RTT) User Interface Table 14-1.
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14.5.1 Real-time Timer Mode Register Name: RTT_MR Address: 0xFFFFFD20 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216.
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14.5.2 Real-time Timer Alarm Register Name: RTT_AR Address: 0xFFFFFD24 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer.
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14.5.3 Real-time Timer Value Register Name: RTT_VR Address: 0xFFFFFD28 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV • CRTV: Current Real-time Value Returns the current value of the Real-time Timer.
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14.5.4 Real-time Timer Status Register Name: RTT_SR Address: 0xFFFFFD2C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS • ALMS: Real-time Alarm Status 0: The Real-time Alarm has not occurred since the last read of RTT_SR. 1: The Real-time Alarm occurred since the last read of RTT_SR.
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15. Periodic Interval Timer (PIT) 15.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 15.2 15.3 Embedded Characteristics  Includes a 20-bit Periodic Counter with less than 1 µs accuracy  Includes a 12-bit Interval Overlay Counter  Real time OS or Linux®/WindowsCE® compliant tick generator Block Diagram Figure 15-1.
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When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS.
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15.5 Periodic Interval Timer (PIT) User Interface Table 15-1.
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15.5.1 Periodic Interval Timer Mode Register Name: PIT_MR Address: 0xFFFFFD30 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 PITIEN 24 PITEN 23 – 22 – 21 – 20 – 19 18 17 16 15 14 13 12 PIV 11 10 9 8 3 2 1 0 PIV 7 6 5 4 PIV • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1).
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15.5.2 Periodic Interval Timer Status Register Name: PIT_SR Address: 0xFFFFFD34 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 PITS • PITS: Periodic Interval Timer Status 0: The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1: The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.
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15.5.3 Periodic Interval Timer Value Register Name: PIT_PIVR Address: 0xFFFFFD38 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer.
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15.5.4 Periodic Interval Timer Image Register Name: PIT_PIIR Address: 0xFFFFFD3C Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
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16. Shutdown Controller (SHDWC) 16.1 Overview The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wakeup detection on debounced input lines. 16.2 Embedded Characteristics  16.3 Shutdown and Wakeup logic: ̶ Software programmable assertion of the SHDN pin ̶ Deassertion Programmable on a WKUP pin level change or on alarm Block Diagram Figure 16-1.
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16.6 Functional Description The Shutdown Controller manages the main power supply. To do so, it is supplied with VDDBU and manages wakeup input pins and one output pin, SHDN. A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter providing the main power supplies of the system, and especially VDDCORE and/or VDDIO. The wakeup inputs (WKUP0) connect to any push-buttons or signal that wake up the system.
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16.7 Shutdown Controller (SHDWC) User Interface Table 16-2.
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16.7.1 Shutdown Control Register Name: SHDW_CR Address: 0xFFFFFD10 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SHDW • SHDW: Shutdown Command 0: No effect. 1: If KEY is correct, asserts the SHDN pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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16.7.2 Shutdown Mode Register Name: SHDW_MR Address: 0xFFFFFD14 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 RTTWKEN 15 14 13 12 11 – 10 – 9 3 – 2 – 1 – 7 6 5 4 CPTWK0 8 – 0 WKMODE0 • WKMODE0: Wakeup Mode 0 Value Wakeup Input Transition Selection 0 0 None.
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16.7.3 Shutdown Status Register Name: SHDW_SR Address: 0xFFFFFD18 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 RTTWK 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WAKEUP0 • WAKEUP0: Wakeup 0 Status 0: No wakeup event occurred on the corresponding wakeup input since the last read of SHDW_SR. 1: At least one wakeup event occurred on the corresponding wakeup input since the last read of SHDW_SR.
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17. General Purpose Backup Register (GPBR) 17.1 Overview The System Controller embeds 4 general-purpose backup registers. 17.2 General Purpose Backup Registers (GPBR) User Interface Table 17-1. Offset 0x0 ... 0xC Register Mapping Register Name General Purpose Backup Register 0 SYS_GPBR0 ... ... General Purpose Backup Register 3 SYS_GPBR 3 Access Reset Read/Write – ... ...
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17.2.
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18. Bus Matrix 18.1 Overview The Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects 5 AHB Masters to 5 AHB Slaves. The Bus Matrix user interface is compliant with the ARM Advanced Peripheral Bus and provides 5 Special Function Registers (MATRIX_SFR) that allow the Bus Matrix to support application-specific features. 18.
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18.4 Arbitration The Bus Matrix provides an arbitration function that reduces latency when conflicting cases occur, i.e., when two or more masters try to access the same slave at the same time. The Bus Matrix arbitration mechanism uses slightly modified round-robin algorithms that grant the bus for the first access to a certain master depending on parameters located in the slave’s Slave Configuration Register.
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18.5 Bus Matrix (MATRIX) User Interface Table 18-1.
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18.5.
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18.5.2 Bus Matrix Slave Configuration Registers Name: MATRIX_SCFG0...
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18.5.
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18.5.4 EBI Chip Select Assignment Register Name: EBI_CSA Address: 0xFFFFEE30 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – EBI_DBPUC 7 6 5 4 3 2 1 0 – – EBI_CS5A EBI_CS4A EBI_CS3A – EBI_CS1A – • EBI_CS1A: EBI Chip Select 1 Assignment 0: EBI Chip Select 1 is assigned to the Static Memory Controller.
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18.5.
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19. External Bus Interface (EBI) 19.1 Overview The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory and SDRAM Controllers are all featured external Memory Controllers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, and SDRAM.
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19.2 Block Diagram Figure 19-1 shows the organization of the External Bus Interface. Figure 19-1.
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19.3 I/O Lines Description Table 19-1.
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Table 19-2. 19.4 EBI Pins and Memory Controllers I/O Lines Connections EBI Pins SDRAMC I/O Lines SMC I/O Lines NWR1/NBS1/CFIOR NBS1 NWR1/NUB A0/NBS0 Not Supported SMC_A0/NLB A1/NBS2/NWR2 Not Supported SMC_A1 A[11:2] SDRAMC_A[9:0] SMC_A[11:2] SDA10 SDRAMC_A10 Not Supported A12 Not Supported SMC_A12 A[14:13] SDRAMC_A[12:11] SMC_A[14:13] A[25:15] Not Supported SMC_A[25:15] D[31:16] D[31:16] D[31:16] D[15:0] D[15:0] D[15:0] Application Example 19.4.
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Table 19-3. EBI Pins and External Static Devices Connections (Continued) Pins of the SMC Interfaced Device 8-bit Static Device 2 x 8-bit Static Devices 16-bit Static Device 4 x 8-bit Static Devices 2 x 16-bit Static Devices 32-bit Static Device NWR0/NWE WE WE(1) WE WE(2) WE WE NWR1/NBS1 – WE(1) NUB WE(2) NUB(3) BE1(5) NUB(4) BE3(5) Pins NWR3/NBS3 – – – WE(2) Notes: 1. NWR1 enables upper byte writes. NWR0 enables lower byte writes. 2. NWRx enables corresponding byte x writes.
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Table 19-4.
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19.4.2 Connection Examples Figure 19-2 shows an example of connections between the EBI and external devices. Figure 19-2.
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19.6 Functional Description The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the external memories or peripheral devices.
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Figure 19-3. CompactFlash Memory Mapping True IDE Alternate Mode Space Offset 0x00E0 0000 True IDE Mode Space Offset 0x00C0 0000 CF Address Space I/O Mode Space Offset 0x0080 0000 Common Memory Mode Space Offset 0x0040 0000 Attribute Memory Mode Space Offset 0x0000 0000 Note: The A22 pin of the EBI is used to drive the REG signal of the CompactFlash Device (except in True IDE mode). Table 19-5.
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Table 19-6.
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Table 19-7. CompactFlash Mode Selection Mode Base Address CFOE CFWE CFIOR CFIOW NRD NWR0_NWE 1 1 I/O Mode 1 1 NRD NWR0_NWE True IDE Mode 0 1 NRD NWR0_NWE Attribute Memory Common Memory 19.6.5.4 Multiplexing of CompactFlash Signals on EBI Pins Table 19-8 and Table 19-9 illustrate the multiplexing of the CompactFlash logic signals with other EBI signals on the EBI pins.
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Figure 19-5. CompactFlash Application Example EBI CompactFlash Connector D[15:0] D[15:0] DIR /OE A25/CFRNW NCS4/CFCS0 _CD1 CD (PIO) _CD2 /OE A[10:0] A[10:0] A22/REG _REG NRD/CFOE _OE NWE/CFWE _WE NWR1/CFIOR _IORD NWR3/CFIOW _IOWR CFCE1 _CE1 CFCE2 _CE2 NWAIT _WAIT 19.6.6 NAND Flash Support The EBI integrates circuitry that interfaces to NAND Flash devices. The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space.
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Figure 19-6. NAND Flash Signal Multiplexing on EBI Pins SMC MUX Logic NCS6 NCS6_NANDOE CS3A NCS7 NCS7_NANDWE NAND Flash Logic CS3A NCS3 NRD NANDOE NANDWE NWR0_NWE The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus. The user should note that any bit on the EBI address bus can also be used for this purpose.
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Figure 19-7. NAND Flash Application Example D[7:0] AD[7:0] A[22:21] ALE CLE NCS3/NANDCS Not Connected EBI NAND Flash NCS6/NANDOE NCS7/NANDWE Note: 144 NOE NWE PIO CE PIO R/B The External Bus Interface is also able to support 16-bit devices.
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19.7 Implementation Examples All the hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check the device availability. 19.7.1 16-bit SDRAM 19.7.1.1 Hardware Configuration D[0..15] A[0..
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19.7.2 32-bit SDRAM 19.7.2.1 Hardware Configuration D[0..31] A[0..14] (Not used A12) U1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A13 SDA10 BA0 BA1 SDA10 BA0 BA1 A14 23 24 25 26 29 30 31 32 33 34 22 35 20 21 36 40 SDCKE SDCK A0 CFIOR_NBS1_NWR1 CAS RAS SDWE SDCKE 37 SDCK 38 1%6 1%6 15 39 CAS RAS 17 18 SDWE 16 19 SDCS_NCS1 U2 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.
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19.7.3 8-bit NAND Flash 19.7.3.1 Hardware Configuration D[0..7] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 10K 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 K9F2G08U0M N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 29 30 31 32 41 42 43 44 N.C N.C N.C N.C N.C N.C PRE N.C N.C N.C N.C N.
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19.7.4 16-bit NAND Flash 19.7.4.1 Hardware Configuration D[0..15] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 34 35 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C 10K MT29F2G16AABWP-ET I/O0 26 I/O1 28 I/O2 30 I/O3 32 I/O4 40 I/O5 42 I/O6 44 I/O7 46 I/O8 27 I/O9 29 I/O10 31 I/O11 33 I/O12 41 I/O13 43 I/O14 45 I/O15 47 N.C PRE N.
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19.7.5 NOR Flash on NCS0 19.7.5.1 Hardware Configuration D[0..15] A[1..
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19.7.6 Compact Flash Figure 19-8. Hardware Configuration MEMORY & I/O MODE D[0..
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19.7.6.1 Software Configuration The following configuration has to be performed:  Assign the EBI CS4 and/or EBI CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the EBI_CS4A or/and EBI_CS5A bit(s) in the EBI Chip Select Assignment Register located in the bus matrix memory space.  The address line A23 is to select I/O (A23=1) or Memory mode (A23=0) and the address line A22 for REG function.
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19.7.7 Compact Flash True IDE Figure 19-9. Hardware Configuration TRUE IDE MODE D[0..
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19.7.7.1 Software Configuration The following configuration has to be performed:  Assign the EBI CS4 and/or EBI CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the EBI_CS4A or/and EBI_CS5A bit(s) in the EBI Chip Select Assignment Register located in the bus matrix memory space.  The address line A21 is to select Alternate True IDE (A21=1) or True IDE (A21=0) modes.
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20. Static Memory Controller (SMC) 20.1 Overview The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or peripheral devices. It has 8 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable.
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20.4 Application Example 20.4.1 Hardware Interface Figure 20-1. SMC Connections to Static Memory Devices D0-D31 A0/NBS0 NWR0/NWE NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 D0 - D7 128K x 8 SRAM D8-D15 D0 - D7 CS NRD NWR0/NWE A2 - A25 A2 - A18 A0 - A16 NRD OE NWR1/NBS1 WE 128K x 8 SRAM D16 - D23 D24-D31 D0 - D7 A0 - A16 NRD Static Memory Controller 20.
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20.6 External Memory Mapping The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of memory. If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see Figure 20-2).
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20.7 Connection to External Devices 20.7.1 Data Bus Width A data bus width of 8, 16, or 32 bits can be selected for each chip select. This option is controlled by the field DBW in SMC_MODE (Mode Register) for the corresponding chip select. Figure 20-3 shows how to connect a 512K x 8-bit memory on NCS2. Figure 20-4 shows how to connect a 512K x 16-bit memory on NCS2. Figure 20-5 shows two 16-bit memories connected as a single 32-bit memory 20.7.
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20.7.2.1 Byte Write Access Byte write access supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte Write Access mode.  For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided. Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory.
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Figure 20-7. Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option) D[15:0] D[15:0] D[31:16] A[25:2] A[23:0] NWE Write Enable NBS0 Low Byte Enable NBS1 High Byte Enable NBS2 SMC NBS3 Read Enable NRD Memory Enable NCS[3] D[31:16] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable Memory Enable 20.7.2.3 Signal Multiplexing Depending on the BAT, only the write signals or the byte select signals are used.
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20.8 Standard Read and Write Protocols In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS3) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR3) in byte write access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..7] chip select lines. 20.8.
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20.8.1.3 Read Cycle The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is equal to: NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD, as well as NRD_CYCLE = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles.
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20.8.1.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior. 20.8.2 Read Mode As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first.
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Figure 20-11. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS tPACC D[31:0] Data Sampling 20.8.3 Write Waveforms The write protocol is similar to the read protocol. It is depicted in Figure 20-12. The write cycle starts with the address setting on the memory address bus. 20.8.3.1 NWE Waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1.
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Figure 20-12. Write Cycle MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NCS NWE_SETUP NCS_WR_SETUP NWE_PULSE NCS_WR_PULSE NWE_HOLD NCS_WR_HOLD NWE_CYCLE 20.8.3.3 Write Cycle The write cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change.
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20.8.3.4 Null Delay Setup and Hold If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write cycles in the same memory (see Figure 20-13). However, for devices that perform write operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed. Figure 20-13.
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20.8.4 Write Mode The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal controls the write operation. 20.8.4.1 Write is Controlled by NWE (WRITE_MODE = 1): Figure 20-14 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus during the pulse and hold steps of the NWE signal.
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20.8.5 Coding Timing Parameters All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according to their type.
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20.9 Automatic Wait States Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or operation conflict. 20.9.1 Chip Select Wait States The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one.
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20.9.2 Early Read Wait State In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select).
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Figure 20-18. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NCS NRD no hold no setup D[31:0] write cycle (WRITE_MODE = 0) Early Read wait state read cycle (READ_MODE = 0 or READ_MODE = 1) Figure 20-19.
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When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next access. The so called “Reload User Configuration Wait State” is used by the SMC to load the new set of parameters to apply to next accesses. The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State.
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20.10.1 READ_MODE Setting the READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal and lasts TDF_CYCLES MCK cycles. When the read operation is controlled by the NCS signal (READ_MODE = 0), the TDF field gives the number of MCK cycles during which the data bus remains busy after the rising edge of NCS.
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Figure 20-21.
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20.10.2 TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. Figure 20-22 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0.
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Figure 20-23. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) read1 hold = 1 read2 controlling signal (NRD) read2 setup = 1 TDF_CYCLES = 6 D[31:0] 5 TDF WAIT STATES read 2 cycle TDF_MODE = 0 (optimization disabled) read1 cycle TDF_CYCLES = 6 Chip Select Wait State Figure 20-24.
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Figure 20-25. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) write2 setup = 1 read1 hold = 1 write2 controlling signal (NWE) TDF_CYCLES = 5 D[31:0] 4 TDF WAIT STATES read1 cycle TDF_CYCLES = 5 Read to Write Wait State write2 cycle TDF_MODE = 0 (optimization disabled) 20.11 External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC.
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20.11.2 Frozen Mode When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 20-26.
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Figure 20-27.
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20.11.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 20-28 and Figure 20-29. After deassertion, the access is completed: the hold step of the access is performed.
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Figure 20-29.
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20.11.4 NWAIT Latency and Read/Write Timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode.
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20.12 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate.
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20.12.2 Switching from (to) Slow Clock Mode to (from) Normal Mode When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters. See Figure 20-32. The external device may not be fast enough to support such timings. Figure 20-33 illustrates the recommended procedure to properly switch from one mode to the other. Figure 20-32.
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20.13 Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes. The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory.
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In page mode, the programming of the read timings is described in Table 20-7:. Table 20-7. Programming of Read Timings in Page Mode Parameter Value Definition READ_MODE ‘x’ No impact NCS_RD_SETUP ‘x’ No impact NCS_RD_PULSE tpa Access time of first access to the page NRD_SETUP ‘x’ No impact NRD_PULSE tsa Access time of subsequent accesses in the page NRD_CYCLE ‘x’ No impact The SMC does not check the coherency of timings.
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Figure 20-35.
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20.14 Static Memory Controller (SMC) User Interface The SMC is programmed using the registers listed in Table 20-8. For each chip select, a set of four registers is used to program the parameters of the external device connected on it. In Table 20-8, “CS_number” denotes the chip select number. 16 bytes (0x10) are required per chip select. The user must complete writing the configuration by writing any one of the SMC_MODE registers. Table 20-8.
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20.14.1 SMC Setup Register Name: SMC_SETUP[0..
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20.14.2 SMC Pulse Register Name: SMC_PULSE[0..
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20.14.3 SMC Cycle Register Name: SMC_CYCLE[0..
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20.14.4 SMC Mode Register Name: SMC_MODE[0..
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• Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. • BAT: Byte Access Type This field is used only if DBW defines a 16- or 32-bit data bus. • 1: Byte write access type: – Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3. – Read operation is controlled using NCS and NRD.
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21. SDRAM Controller (SDRAMC) 21.1 Overview The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit SDRAM device. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. The SDRAM Controller supports a read or write burst length of one location.
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21.3 Application Example 21.3.1 Software Interface The SDRAM address space is organized into banks, rows, and columns. The SDRAM controller allows mapping different memory types according to the values set in the SDRAMC configuration register. The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to the user. Table 212 to Table 21-7 illustrate the SDRAM device memory mapping seen by the user in correlation with the device structure. Various configurations are illustrated.
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21.3.1.2 16-bit Memory Data Bus Width Table 21-5. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 Bk[1:0] 13 12 11 10 9 8 7 6 Row[10:0] Bk[1:0] 4 3 2 1 M0 Column[9:0] Row[10:0] 0 M0 Column[8:0] Row[10:0] Bk[1:0] 5 Column[7:0] Row[10:0] Bk[1:0] Table 21-6.
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21.4 Product Dependencies 21.4.1 SDRAM Device Initialization The initialization sequence is generated by software. The SDRAM devices are initialized by the following sequence: 1. SDRAM features must be set in the configuration register: asynchronous timings (TRC, TRAS, etc.), number of columns, rows, CAS latency, and the data bus width. 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self refresh (PASR) must be set in the Low Power Register. 3.
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Figure 21-1. SDRAM Device Initialization Sequence SDCKE tRP tRC tMRD SDCK SDRAMC_A[9:0] A10 SDRAMC_A[12:11] SDCS RAS CAS SDWE NBS Inputs Stable for 200 μsec Precharge All Banks 1st Auto-refresh 8th Auto-refresh MRS Command Valid Command 21.4.2 I/O Lines The pins used for interfacing the SDRAM Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the SDRAM Controller pins to their peripheral function.
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21.5 Functional Description 21.5.1 SDRAM Controller Write Cycle The SDRAM Controller allows burst access or single access. In both cases, the SDRAM controller keeps track of the active row in each bank, thus maximizing performance. To initiate a burst access, the SDRAM Controller uses the transfer type signal provided by the master requesting the access. If the next access is a sequential write access, writing to the SDRAM device is carried out.
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21.5.2 SDRAM Controller Read Cycle The SDRAM Controller allows burst access, incremental burst of unspecified length or single access. In all cases, the SDRAM Controller keeps track of the active row in each bank, thus maximizing performance of the SDRAM. If row and bank addresses do not match the previous row/bank address, then the SDRAM controller automatically generates a precharge command, activates the new row and starts the read command.
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21.5.3 Border Management When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAM controller generates a precharge command, activates the new row and initiates a read or write command. To comply with SDRAM timing parameters, an additional clock cycle is inserted between the precharge/active (tRP) command and the active/read (tRCD) command. This is described in Figure 21-4 below. Figure 21-4.
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21.5.4 SDRAM Controller Refresh Cycles An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refresh automatically. The SDRAM Controller generates these auto-refresh commands periodically. An internal timer is loaded with the value in the register SDRAMC_TR that indicates the number of clock cycles between refresh cycles.
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21.5.5 Power Management Three low-power modes are available:  Self-refresh Mode: The SDRAM executes its own Auto-refresh cycle without control of the SDRAM Controller. Current drained by the SDRAM is very low.  Powerdown Mode: Auto-refresh cycles are controlled by the SDRAM Controller. Between auto-refresh cycles, the SDRAM is in powerdown. Current drained in Powerdown mode is higher than in Self-refresh Mode.
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21.5.5.2 Low-power Mode This mode is selected by programming the LPCB field to 2 in the SDRAMC Low Power Register. Power consumption is greater than in self-refresh mode. All the input and output buffers of the SDRAM device are deactivated except SDCKE, which remains low. In contrast to self-refresh mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64 ms for a whole device refresh operation).
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21.5.5.3 Deep Powerdown Mode This mode is selected by programming the LPCB field to 3 in the SDRAMC Low Power Register. When this mode is activated, all internal voltage generators inside the SDRAM are stopped and all data is lost. When this mode is enabled, the application must not access to the SDRAM until a new initialization sequence is done (See “SDRAM Device Initialization” on page 196). This is described in Figure 21-8. Figure 21-8.
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21.6 SDRAM Controller (SDRAMC) User Interface Table 21-8.
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21.6.1 SDRAMC Mode Register Register SDRAMC_MR Address: 0xFFFFEA00 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 0 MODE • MODE: SDRAMC Command Mode This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed. Value Description 0 0 0 Normal mode. Any access to the SDRAM is decoded normally.
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21.6.2 SDRAMC Refresh Timer Register Register: SDRAMC_TR Address: 0xFFFFEA04 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 COUNT 3 2 COUNT • COUNT: SDRAMC Refresh Timer Count This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated.
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21.6.3 SDRAMC Configuration Register Register: SDRAMC_CR Address: 0xFFFFEA08 Access: Read/Write 31 30 29 28 27 26 TXSR 23 22 21 20 19 18 TRCD 15 14 13 6 12 11 17 16 10 9 8 TWR 5 CAS 4 NB 3 Reset value is 8 column bits. Value Column Bits 0 0 8 0 1 9 1 0 10 1 1 11 • NR: Number of Row Bits Reset value is 11 row bits. Value Row Bits 0 0 11 0 1 12 1 0 13 1 1 Reserved • NB: Number of Banks Reset value is two banks.
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• CAS: CAS Latency Reset value is two cycles. In the SDRAMC, only a CAS latency of one, two and three cycles is managed. Value CAS Latency (Cycles) 0 0 Reserved 0 1 1 1 0 2 1 1 3 • DBW: Data Bus Width Reset value is 16 bits 0: Data bus width is 32 bits. 1: Data bus width is 16 bits. • TWR: Write Recovery Delay Reset value is two cycles. This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15. • TRC: Row Cycle Delay Reset value is seven cycles.
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21.6.4 SDRAMC Low Power Register Register: SDRAMC_LPR Address: 0xFFFFEA10 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 12 11 10 9 7 – 6 5 PASR TIMEOUT DS 4 3 – 8 TCSR 2 – 1 0 LPCB • LPCB: Low-power Configuration Bits Value Description 00 Low Power Feature is inhibited: no Powerdown, Self-refresh or Deep Powerdown command is issued to the SDRAM device.
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21.6.5 SDRAMC Interrupt Enable Register Register: SDRAMC_IER Address: 0xFFFFEA14 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES • RES: Refresh Error Status 0: No effect. 1: Enables the refresh error interrupt.
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21.6.6 SDRAMC Interrupt Disable Register Register: SDRAMC_IDR Address: 0xFFFFEA18 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES • RES: Refresh Error Status 0: No effect. 1: Disables the refresh error interrupt.
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21.6.7 SDRAMC Interrupt Mask Register Register: SDRAMC_IMR Address: 0xFFFFEA1C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES • RES: Refresh Error Status 0: The refresh error interrupt is disabled. 1: The refresh error interrupt is enabled.
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21.6.8 SDRAMC Interrupt Status Register Register: SDRAMC_ISR Address: 0xFFFFEA20 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES • RES: Refresh Error Status 0: No refresh error has been detected since the register was last read. 1: A refresh error has been detected since the register was last read.
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21.6.9 SDRAMC Memory Device Register Register: SDRAMC_MDR Address: 0xFFFFEA24 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 0 MD • MD: Memory Device Type Value Description 00 SDRAM 01 Low-power SDRAM 10 Reserved 11 Reserved.
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22. Peripheral DMA Controller (PDC) 22.1 Overview The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. The link between the PDC and a serial peripheral is operated by the AHB to ABP bridge. The PDC contains 19 channels. The full-duplex peripherals feature 18 mono directional channels used in pairs (transmit only or receive only). The half-duplex peripherals feature 1 bi-directional channels.
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22.2 Block Diagram Figure 22-1.
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22.3 Functional Description 22.3.1 Configuration The PDC channel user interface enables the user to configure and control data transfers for each channel. The user interface of each PDC channel is integrated into the associated peripheral user interface. The user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (RPR, RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR).
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22.3.4 Data Transfers The serial peripheral triggers its associated PDC channels’ transfers using transmit enable (TXEN) and receive enable (RXEN) flags in the transfer control register integrated in the peripheral’s user interface. When the peripheral receives an external data, it sends a Receive Ready signal to its PDC receive channel which then requests access to the Matrix. When access is granted, the PDC receive channel starts reading the peripheral Receive Holding Register (RHR).
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22.4 Peripheral DMA Controller (PDC) User Interface Table 22-1.
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22.4.1 Receive Pointer Register Name: PERIPH_RPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXPTR 23 22 21 20 RXPTR 15 14 13 12 RXPTR 7 6 5 4 RXPTR • RXPTR: Receive Pointer Register RXPTR must be set to receive buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
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22.4.2 Receive Counter Register Name: PERIPH_RCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXCTR 7 6 5 4 RXCTR • RXCTR: Receive Counter Register RXCTR must be set to receive buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
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22.4.3 Transmit Pointer Register Name: PERIPH_TPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXPTR 23 22 21 20 TXPTR 15 14 13 12 TXPTR 7 6 5 4 TXPTR • TXPTR: Transmit Counter Register TXPTR must be set to transmit buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
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22.4.4 Transmit Counter Register Name: PERIPH_TCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXCTR 7 6 5 4 TXCTR • TXCTR: Transmit Counter Register TXCTR must be set to transmit buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
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22.4.5 Receive Next Pointer Register Name: PERIPH_RNPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXNPTR 23 22 21 20 RXNPTR 15 14 13 12 RXNPTR 7 6 5 4 RXNPTR • RXNPTR: Receive Next Pointer RXNPTR contains next receive buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
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22.4.6 Receive Next Counter Register Name: PERIPH_RNCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXNCTR 7 6 5 4 RXNCTR • RXNCTR: Receive Next Counter RXNCTR contains next receive buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
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22.4.7 Transmit Next Pointer Register Name: PERIPH_TNPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXNPTR 23 22 21 20 TXNPTR 15 14 13 12 TXNPTR 7 6 5 4 TXNPTR • TXNPTR: Transmit Next Pointer TXNPTR contains next transmit buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
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22.4.8 Transmit Next Counter Register Name: PERIPH_TNCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXNCTR 7 6 5 4 TXNCTR • TXNCTR: Transmit Counter Next TXNCTR contains next transmit buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
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22.4.9 Transfer Control Register Name: PERIPH_PTCR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 TXTDIS 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXTDIS 0 RXTEN • RXTEN: Receiver Transfer Enable 0: No effect. 1: Enables PDC receiver channel requests if RXTDIS is not set.
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22.4.10 Transfer Status Register Name: PERIPH_PTSR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RXTEN • RXTEN: Receiver Transfer Enable 0: PDC Receiver channel requests are disabled. 1: PDC Receiver channel requests are enabled. • TXTEN: Transmitter Transfer Enable 0: PDC Transmitter channel requests are disabled.
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23. Clock Generator (CKGR) 23.1 Overview The Clock Generator is made up of 2 PLL, a Main Oscillator, and a 32.768 kHz low-power Oscillator. It provides the following clocks:  SLCK, the Slow Clock, which is the only permanent clock within the system  MAINCK is the output of the Main Oscillator The Clock Generator User Interface is embedded within the Power Management Controller one and is described in Section 24.9. However, the Clock Generator registers are named CKGR_. 23.
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23.3.1 Main Oscillator Connections The Clock Generator integrates a Main Oscillator that is designed for a 3 to 20 MHz fundamental crystal. The typical crystal connection is illustrated in Figure 23-3. The 1 k Ω resistor is only required for crystals with frequencies lower than 8 MHz. For further details on the electrical characteristics of the Main Oscillator, see the section “DC Characteristics” of the product datasheet. Figure 23-3.
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stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can be determined. 23.3.5 Main Oscillator Bypass The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the external clock signal on the XIN pin.
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23.4.1 PLL Filter The PLL requires connection to an external second-order filter through the PLLRCA and/or PLLRCB pin. Figure 23-5 shows a schematic of these filters. Figure 23-5. PLL Capacitors and Resistors PLLRC PLL R C2 C1 GND Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of the PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be found between output signal overshoot and startup time. 23.4.
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24. Power Management Controller (PMC) 24.1 Overview The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor. The Power Management Controller provides the following clocks: 24.2  MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device.
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24.3 Processor Clock Controller The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock can be disabled by writing the System Clock Disable Register (PMC_SCDR). The status of this clock (at least for debug purposes) can be read in the System Clock Status Register (PMC_SCSR). The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt.
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24.6 Programmable Clock Output Controller The PMC controls 4 signals to be output on external pins PCKx. Each signal can be independently programmed via the PMC_PCKx registers. PCKx can be independently selected between the Slow clock, the PLL A output, the PLL B output and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx.
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The PLLACOUNT field specifies the number of slow clock cycles before LOCKA bit is set in the PMC_SR after CKGR_PLLAR has been written. Once CKGR_PLLAR has been written, the user is obliged to wait for the LOCKA bit to be set in the PMC_SR. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to LOCKA has been enabled in the PMC_IER. All parameters in CKGR_PLLAR can be programmed in a single write operation.
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The MDIV field is used to control the Master Clock divider. It is possible to choose between different values (0, 1, 2). The Master Clock output is Processor Clock divided by 1, 2 or 4, depending on the value programmed in MDIV. By default, MDIV is set to 0, which indicates that the Processor Clock is equal to the Master Clock. Once the PMC_MCKR has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR.
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PCKRDYx has been enabled in the PMC_IER. All parameters in PMC_PCKx can be programmed in a single write operation. If the CSS and PRES parameters are to be modified, the corresponding Programmable clock must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the Programmable clock and wait for the PCKRDYx bit to be set. Code Example: write_register(PMC_PCK0,0x00000015) Programmable clock 0 is main clock divided by 32. 7.
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24.8 Clock Switching Details 24.8.1 Master Clock Switching Timings Table 24-1 and Table 24-2 give the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 24-1. Clock Switching Timings (Worst Case) From Main Clock SLCK PLL Clock – 4 x SLCK + 2.5 x Main Clock 0.5 x Main Clock + 4.
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24.8.2 Clock Switching Waveforms Figure 24-3. Switch Master Clock from Slow Clock to PLL Clock Slow Clock PLL Clock LOCK MCKRDY Master Clock Write PMC_MCKR Figure 24-4.
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Figure 24-5. Change PLLA Programming Slow Clock PLLA Clock LOCK MCKRDY Master Clock Slow Clock Write CKGR_PLLAR Figure 24-6.
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Figure 24-7.
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24.9 Power Management Controller (PMC) User Interface Table 24-3.
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24.9.1 PMC System Clock Enable Register Name: PMC_SCER Address: 0xFFFFFC00 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – HCK1 HCK0 15 14 13 12 11 10 9 8 – – – – PCK3 PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – – – – – – • UDP: USB Device Port Clock Enable 0: No effect. 1: Enables the 48 MHz clock of the USB Device Port. • PCKx: Programmable Clock x Output Enable 0: No effect.
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24.9.2 PMC System Clock Disable Register Name: PMC_SCDR Address: 0xFFFFFC04 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – HCK1 HCK0 15 14 13 12 11 10 9 8 – – – – PCK3 PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – – – – – PCK • PCK: Processor Clock Disable 0: No effect. 1: Disables the Processor clock. This is used to enter the processor in Idle Mode.
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24.9.3 PMC System Clock Status Register Name: PMC_SCSR Address: 0xFFFFFC08 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – HCK1 HCK0 15 14 13 12 11 10 9 8 – – – – PCK3 PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – – – – – PCK • PCK: Processor Clock Status 0: The Processor clock is disabled. 1: The Processor clock is enabled.
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24.9.4 PMC Peripheral Clock Enable Register Name: PMC_PCER Address: 0xFFFFFC10 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 - - • PIDx: Peripheral Clock x Enable 0: No effect.
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24.9.5 PMC Peripheral Clock Disable Register Name: PMC_PCDR Address: 0xFFFFFC14 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 - - • PIDx: Peripheral Clock x Disable 0: No effect.
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24.9.
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24.9.7 PMC Clock Generator Main Oscillator Register Name: CKGR_MOR Address: 0xFFFFFC20 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 – 1 OSCBYPASS 0 MOSCEN OSCOUNT 7 – 6 – 5 – 4 – • MOSCEN: Main Oscillator Enable A crystal must be connected between XIN and XOUT. 0: The Main Oscillator is disabled. 1: The Main Oscillator is enabled. OSCBYPASS must be set to 0.
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24.9.8 PMC Clock Generator Main Clock Frequency Register Name: CKGR_MCFR Address: 0xFFFFFC24 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 MAINRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF • MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. • MAINRDY: Main Clock Ready 0: MAINF value is not valid or the Main Oscillator is disabled.
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24.9.9 PMC Clock Generator PLL A Register Name: CKGR_PLLAR Address: 0xFFFFFC28 Access: Read/Write 31 – 30 – 29 1 28 – 27 – 26 25 MULA 24 23 22 21 20 19 18 17 16 10 9 8 2 1 0 MULA 15 14 13 12 11 OUTA 7 PLLACOUNT 6 5 4 3 DIVA Possible limitations on PLL A input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR.
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24.9.10 PMC Clock Generator PLL B Register Name: CKGR_PLLBR Address: 0xFFFFFC2C Access: Read/Write 31 – 30 – 29 23 22 21 28 27 – 26 25 MULB 24 20 19 18 17 16 10 9 8 2 1 0 USBDIV MULB 15 14 13 12 11 OUTB 7 PLLBCOUNT 6 5 4 3 DIVB Possible limitations on PLL B input frequencies and multiplier factors should be checked before using the PMC.
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24.9.
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24.9.
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24.9.
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24.9.
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24.9.15 PMC Status Register Name: PMC_SR Address: 0xFFFFFC68 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – PCKRDY3 PCKRDY2 PCKRDY1 PCKRDY0 7 6 5 4 3 2 1 0 – – – – MCKRDY LOCKB LOCKA MOSCS • MOSCS: MOSCS Flag Status 0: Main oscillator is not stabilized. 1: Main oscillator is stabilized. • LOCKA: PLL A Lock Status 0: PLL A is not locked 1: PLL A is locked.
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24.9.
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24.9.17 PLL Charge Pump Current Register Name: PMC_PLLICPR Address: 0xFFFFFC80 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – ICPPLLB 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – ICPPLLA • ICPPLLA: Charge pump current Must be set to 1. • ICPPLLB: Charge pump current Must be set to 1.
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25. Watchdog Timer (WDT) 25.1 Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 25.2 25.
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25.4 Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
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Figure 25-2.
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25.5 Watchdog Timer (WDT) User Interface Table 25-1.
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25.5.1 Watchdog Timer Control Register Name: WDT_CR Address: 0xFFFFFD40 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WDRSTT • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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25.5.2 Watchdog Timer Mode Register Name: WDT_MR Address: 0xFFFFFD44 Access: Read-write Once 31 30 23 29 WDIDLEHLT 28 WDDBGHLT 27 21 20 19 11 22 26 25 24 18 17 16 10 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. • WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt.
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• WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer.
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25.5.3 Watchdog Timer Status Register Name: WDT_SR Address: 0xFFFFFD48 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.
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26. Advanced Interrupt Controller (AIC) 26.1 Overview The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and realtime overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor.
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26.4 AIC Detailed Block Diagram Figure 26-3. AIC Detailed Block Diagram Advanced Interrupt Controller FIQ PIO Controller Fast Interrupt Controller External Source Input Stage ARM Processor nFIQ nIRQ IRQ0-IRQn Embedded Peripherals Interrupt Priority Controller Fast Forcing PIOIRQ Internal Source Input Stage Processor Clock Power Management Controller User Interface Wake Up APB 26.5 I/O Line Description Table 26-1. 26.
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the interrupt. This is performed by reading successively the status registers of the above mentioned system peripherals. The interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines. The external interrupt lines can be connected directly, or through the PIO Controller. The PIO Controllers are considered as user peripherals in the scope of interrupt handling.
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26.7.1.4 Interrupt Status For each interrupt, the AIC operation originates in AIC_IPR (Interrupt Pending Register) and its mask in AIC_IMR (Interrupt Mask Register). AIC_IPR enables the actual activity of the sources, whether masked or not. The AIC_ISR reads the number of the current interrupt (see “Priority Controller” on page 276) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor.
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This section addresses only the hardware resynchronizations. It gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the processor. The resynchronization time depends on the programming of the interrupt source and on its type (internal or external).
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26.7.2.4 Internal Interrupt Level Sensitive Source Figure 26-9. Internal Interrupt Level Sensitive Source MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active 26.7.3 Normal Interrupt 26.7.3.1 Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast Forcing).
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26.7.3.3 Interrupt Vectoring The interrupt handler addresses corresponding to each interrupt source can be stored in the registers AIC_SVR1 to AIC_SVR31 (Source Vector Register 1 to 31). When the processor reads AIC_IVR (Interrupt Vector Register), the value written into AIC_SVR corresponding to the current interrupt is returned.
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is saved if it is to be restored directly into the program counter at the end of the interrupt. For example, the instruction SUB PC, LR, #4 may be used. 5. Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re-assertion of the nIRQ to be taken into account by the core. This can happen if an interrupt with a higher priority than the current interrupt occurs. 6.
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26.7.4.4 Fast Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and associated status bits. Assuming that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2.
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If the interrupt source is programmed in level-sensitive mode and an active level is sampled, Fast Forcing results in the assertion of the nFIQ line to the core. If the interrupt source is programmed in edge-triggered mode and an active edge is detected, Fast Forcing results in the assertion of the nFIQ line to the core. The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending Register (AIC_IPR).
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An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the AIC_ISR. Extra AIC_IVR reads perform the same operations. However, it is recommended to not stop the processor between the read and the write of AIC_IVR of the interrupt service routine to make sure the debugger does not modify the AIC context. To summarize, in normal operating mode, the read of AIC_IVR performs the following operations within the AIC: 1. Calculates active interrupt (higher than current or spurious).
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26.8 Advanced Interrupt Controller (AIC) User Interface 26.8.1 Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor support only a ± 4-Kbyte offset. Table 26-2. Register Mapping Offset Register Name Access Reset 0x00 Source Mode Register 0 AIC_SMR0 Read/Write 0x0 0x04 Source Mode Register 1 AIC_SMR1 Read/Write 0x0 ... ... ... ... ...
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26.8.2 AIC Source Mode Register Name: AIC_SMR0..AIC_SMR31 Address: 0xFFFFF000 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 4 3 2 1 0 – – – 5 SRCTYPE PRIOR • PRIOR: Priority Level Programs the priority level for all sources except FIQ source (source 0). The priority level can be between 0 (lowest) and 7 (highest).
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26.8.3 AIC Source Vector Register Name: AIC_SVR0..AIC_SVR31 Address: 0xFFFFF080 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VECTOR 23 22 21 20 VECTOR 15 14 13 12 VECTOR 7 6 5 4 VECTOR • VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source.
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26.8.4 AIC Interrupt Vector Register Name: AIC_IVR Address: 0xFFFFF100 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IRQV 23 22 21 20 IRQV 15 14 13 12 IRQV 7 6 5 4 IRQV • IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt.
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26.8.5 AIC FIQ Vector Register Name: AIC_FVR Address: 0xFFFFF104 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU.
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26.8.6 AIC Interrupt Status Register Name: AIC_ISR Address: 0xFFFFF108 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 4 3 2 1 0 7 6 5 – – – IRQID • IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number.
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26.8.7 AIC Interrupt Pending Register Name: AIC_IPR Address: 0xFFFFF10C Access: Read-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Pending 0: Corresponding interrupt is not pending.
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26.8.8 AIC Interrupt Mask Register Name: AIC_IMR Address: 0xFFFFF110 Access: Read-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Mask 0: Corresponding interrupt is disabled.
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26.8.9 AIC Core Interrupt Status Register Name: AIC_CISR Address: 0xFFFFF114 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – NIRQ NFIQ • NFIQ: NFIQ Status 0: nFIQ line is deactivated. 1: nFIQ line is active. • NIRQ: NIRQ Status 0: nIRQ line is deactivated. 1: nIRQ line is active.
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26.8.10 AIC Interrupt Enable Command Register Name: AIC_IECR Address: 0xFFFFF120 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Enable 0: No effect.
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26.8.11 AIC Interrupt Disable Command Register Name: AIC_IDCR Address: 0xFFFFF124 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Disable 0: No effect.
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26.8.12 AIC Interrupt Clear Command Register Name: AIC_ICCR Address: 0xFFFFF128 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Clear 0: No effect.
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26.8.13 AIC Interrupt Set Command Register Name: AIC_ISCR Address: 0xFFFFF12C Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Set 0: No effect.
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26.8.14 AIC End of Interrupt Command Register Name: AIC_EOICR Address: 0xFFFFF130 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – – The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete.
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26.8.15 AIC Spurious Interrupt Vector Register Name: AIC_SPU Address: 0xFFFFF134 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SIVR 23 22 21 20 SIVR 15 14 13 12 SIVR 7 6 5 4 SIVR • SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt.
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26.8.16 AIC Debug Control Register Name: AIC_DCR Address: 0xFFFFF138 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – GMSK PROT • PROT: Protection Mode 0: The Protection Mode is disabled. 1: The Protection Mode is enabled. • GMSK: General Mask 0: The nIRQ and nFIQ lines are normally controlled by the AIC.
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26.8.17 AIC Fast Forcing Enable Register Name: AIC_FFER Address: 0xFFFFF140 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – • SYS, PID2-PID31: Fast Forcing Enable 0: No effect.
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26.8.18 AIC Fast Forcing Disable Register Name: AIC_FFDR Address: 0xFFFFF144 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – • SYS, PID2-PID31: Fast Forcing Disable 0: No effect.
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26.8.
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27. Debug Unit (DBGU) 27.1 Overview The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel’s ARM-based systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. The Debug Unit two-pin UART can be used stand-alone for general purpose serial communication.
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27.3 Block Diagram Figure 27-1. Debug Unit Functional Block Diagram Peripheral Bridge Peripheral DMA Controller APB Debug Unit DTXD Transmit Power Management Controller MCK Parallel Input/ Output Baud Rate Generator Receive DRXD COMMRX ARM Processor COMMTX DCC Handler Chip ID nTRST ICE Access Handler Interrupt Control dbgu_irq Power-on Reset force_ntrst Table 27-1.
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27.4 Product Dependencies 27.4.1 I/O Lines Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit. 27.4.2 Power Management Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller. In this case, the programmer must first configure the PMC to enable the Debug Unit clock.
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27.5.2 Receiver 27.5.2.1 Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped.
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Figure 27-6. Receiver Ready DRXD S D0 D1 D2 D3 D4 D5 D6 D7 D0 S P D1 D2 D3 D4 D5 D6 D7 P RXRDY Read DBGU_RHR 27.5.2.4 Receiver Overrun If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1. Figure 27-7.
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27.5.3 Transmitter 27.5.3.1 Transmitter Reset, Enable and Disable After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register DBGU_THR before actually starting the transmission. The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1.
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Figure 27-11. Transmitter Control DBGU_THR Data 0 Data 1 Shift Register DTXD Data 0 S Data 0 Data 1 P stop S Data 1 P stop TXRDY TXEMPTY Write Data 0 in DBGU_THR Write Data 1 in DBGU_THR 27.5.4 Peripheral Data Controller Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a Peripheral Data Controller (PDC) channel.
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Figure 27-12. Test Modes Automatic Echo RXD Receiver Transmitter Disabled TXD Local Loopback Disabled Receiver RXD VDD Disabled Transmitter Remote Loopback Receiver Transmitter TXD VDD Disabled Disabled RXD TXD 27.5.6 Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator.
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27.5.7 Chip Identifier The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only.
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27.6 Debug Unit (DBGU) User Interface Table 27-2.
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27.6.1 Debug Unit Control Register Name: DBGU_CR Address: 0xFFFFF200 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – • RSTRX: Reset Receiver 0: No effect. 1: The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
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27.6.
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27.6.
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27.6.
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27.6.
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27.6.6 Debug Unit Status Register Name: DBGU_SR Address: 0xFFFFF214 Access: Read-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY • RXRDY: Receiver Ready 0: No character has been received since the last read of the DBGU_RHR or the receiver is disabled.
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• TXBUFE: Transmission Buffer Empty 0: The buffer empty signal from the transmitter PDC channel is inactive. 1: The buffer empty signal from the transmitter PDC channel is active. • RXBUFF: Receive Buffer Full 0: The buffer full signal from the receiver PDC channel is inactive. 1: The buffer full signal from the receiver PDC channel is active. • COMMTX: Debug Communication Channel Write Status 0: COMMTX from the ARM processor is inactive. 1: COMMTX from the ARM processor is active.
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27.6.7 Debug Unit Receiver Holding Register Name: DBGU_RHR Address: 0xFFFFF218 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last received character if RXRDY is set.
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27.6.8 Debug Unit Transmit Holding Register Name: DBGU_THR Address: 0xFFFFF21C Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
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27.6.
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27.6.10 Debug Unit Chip ID Register Name: DBGU_CIDR Address: 0xFFFFF240 Access: Read-only 31 30 29 EXT 23 28 27 26 NVPTYP 22 21 20 19 18 ARCH 15 14 13 6 24 17 16 9 8 1 0 SRAMSIZ 12 11 10 NVPSIZ2 7 25 ARCH NVPSIZ 5 4 3 EPROC 2 VERSION • VERSION: Version of the Device Current version of the device.
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• NVPSIZ2 Second Nonvolatile Program Memory Size Value Size 0 0 0 0 None 0 0 0 1 8 Kbytes 0 0 1 0 16 Kbytes 0 0 1 1 32 Kbytes 0 1 0 0 Reserved 0 1 0 1 64 Kbytes 0 1 1 0 Reserved 0 1 1 1 128 Kbytes 1 0 0 0 Reserved 1 0 0 1 256 Kbytes 1 0 1 0 512 Kbytes 1 0 1 1 Reserved 1 1 0 0 1024 Kbytes 1 1 0 1 Reserved 1 1 1 0 2048 Kbytes 1 1 1 1 Reserved • SRAMSIZ: Internal SRAM Size Value 322 Size 0 0 0 0 Reserved 0 0 0 1 1 Kby
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• ARCH: Architecture Identifier Value Hex Bin Architecture 0x19 0001 1001 AT91SAM9xx Series 0x29 0010 1001 AT91SAM9XExx Series 0x34 0011 0100 AT91x34 Series 0x37 0011 0111 CAP7 Series 0x39 0011 1001 CAP9 Series 0x3B 0011 1011 CAP11 Series 0x40 0100 0000 AT91x40 Series 0x42 0100 0010 AT91x42 Series 0x55 0101 0101 AT91x55 Series 0x60 0110 0000 AT91SAM7Axx Series 0x61 0110 0001 AT91SAM7AQxx Series 0x63 0110 0011 AT91x63 Series 0x70 0111 0000 AT91SAM7Sxx Series 0x71 01
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27.6.11 Debug Unit Chip ID Extension Register Name: DBGU_EXID Address: 0xFFFFF244 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID • EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0.
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27.6.12 Debug Unit Force NTRST Register Name: DBGU_FNR Address: 0xFFFFF248 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – FNTRST • FNTRST: Force NTRST 0: NTRST of the ARM processor’s TAP controller is driven by the power_on_reset signal. 1: NTRST of the ARM processor’s TAP controller is held low.
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28. Peripheral Input/Output Controller (PIO) 28.1 Overview The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface.
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28.2 Block Diagram Figure 28-1. Block Diagram PIO Controller AIC PMC PIO Interrupt PIO Clock Data, Enable Up to 32 peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to 32 pins Up to 32 peripheral IOs Embedded Peripheral PIN 31 APB Figure 28-2.
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28.3 Product Dependencies 28.3.1 Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e.
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28.4 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 28-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 28-3.
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28.4.1 Pull-up Resistor Control Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled.
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manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line. 28.4.5 Synchronous Data Output Controlling all parallel busses using several PIOs requires two successive write operations in the PIO_SODR and PIO_CODR.
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28.4.8 Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral. Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 28.4.
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When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled. Figure 28-6.
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28.5 I/O Lines Programming Example The programing example as shown in Table 28-1 below is used to define the following configuration.
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28.6 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 28-2.
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Table 28-2. Register Mapping (Continued) Offset Register Name Access Reset 0x007C–0x009C Reserved – – – 0x00A0 Output Write Enable PIO_OWER Write-only – 0x00A4 Output Write Disable PIO_OWDR Write-only – 0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000 0x00AC Reserved – – – Notes: 1. Reset value of PIO_PSR depends on the product implementation. 2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3.
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28.6.1 PIO Controller PIO Enable Register Name: PIO_PER Address: 0xFFFFF400 (PIOA), 0xFFFFF600 (PIOB), 0xFFFFF800 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Enable 0: No effect.
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28.6.2 PIO Controller PIO Disable Register Name: PIO_PDR Address: 0xFFFFF404 (PIOA), 0xFFFFF604 (PIOB), 0xFFFFF804 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Disable 0: No effect.
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28.6.3 PIO Controller PIO Status Register Name: PIO_PSR Address: 0xFFFFF408 (PIOA), 0xFFFFF608 (PIOB), 0xFFFFF808 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Status 0: PIO is inactive on the corresponding I/O line (peripheral is active).
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28.6.4 PIO Controller Output Enable Register Name: PIO_OER Address: 0xFFFFF410 (PIOA), 0xFFFFF610 (PIOB), 0xFFFFF810 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Enable 0: No effect. 1: Enables the output on the I/O line.
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28.6.5 PIO Controller Output Disable Register Name: PIO_ODR Address: 0xFFFFF414 (PIOA), 0xFFFFF614 (PIOB), 0xFFFFF814 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Disable 0: No effect. 1: Disables the output on the I/O line.
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28.6.6 PIO Controller Output Status Register Name: PIO_OSR Address: 0xFFFFF418 (PIOA), 0xFFFFF618 (PIOB), 0xFFFFF818 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Status 0: The I/O line is a pure input. 1: The I/O line is enabled in output.
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28.6.7 PIO Controller Input Filter Enable Register Name: PIO_IFER Address: 0xFFFFF420 (PIOA), 0xFFFFF620 (PIOB), 0xFFFFF820 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filter Enable 0: No effect.
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28.6.8 PIO Controller Input Filter Disable Register Name: PIO_IFDR Address: 0xFFFFF424 (PIOA), 0xFFFFF624 (PIOB), 0xFFFFF824 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filter Disable 0: No effect.
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28.6.9 PIO Controller Input Filter Status Register Name: PIO_IFSR Address: 0xFFFFF428 (PIOA), 0xFFFFF628 (PIOB), 0xFFFFF828 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filer Status 0: The input glitch filter is disabled on the I/O line.
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28.6.10 PIO Controller Set Output Data Register Name: PIO_SODR Address: 0xFFFFF430 (PIOA), 0xFFFFF630 (PIOB), 0xFFFFF830 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Set Output Data 0: No effect. 1: Sets the data to be driven on the I/O line.
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28.6.11 PIO Controller Clear Output Data Register Name: PIO_CODR Address: 0xFFFFF434 (PIOA), 0xFFFFF634 (PIOB), 0xFFFFF834 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Set Output Data 0: No effect. 1: Clears the data to be driven on the I/O line.
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28.6.12 PIO Controller Output Data Status Register Name: PIO_ODSR Address: 0xFFFFF438 (PIOA), 0xFFFFF638 (PIOB), 0xFFFFF838 (PIOC) Access: Read-only or Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0: The data to be driven on the I/O line is 0.
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28.6.13 PIO Controller Pin Data Status Register Name: PIO_PDSR Address: 0xFFFFF43C (PIOA), 0xFFFFF63C (PIOB), 0xFFFFF83C (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0: The I/O line is at level 0. 1: The I/O line is at level 1.
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28.6.14 PIO Controller Interrupt Enable Register Name: PIO_IER Address: 0xFFFFF440 (PIOA), 0xFFFFF640 (PIOB), 0xFFFFF840 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Enable 0: No effect.
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28.6.15 PIO Controller Interrupt Disable Register Name: PIO_IDR Address: 0xFFFFF444 (PIOA), 0xFFFFF644 (PIOB), 0xFFFFF844 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Disable 0: No effect.
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28.6.16 PIO Controller Interrupt Mask Register Name: PIO_IMR Address: 0xFFFFF448 (PIOA), 0xFFFFF648 (PIOB), 0xFFFFF848 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Mask 0: Input Change Interrupt is disabled on the I/O line.
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28.6.
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28.6.18 PIO Multi-driver Enable Register Name: PIO_MDER Address: 0xFFFFF450 (PIOA), 0xFFFFF650 (PIOB), 0xFFFFF850 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi Drive Enable 0: No effect. 1: Enables Multi Drive on the I/O line.
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28.6.19 PIO Multi-driver Disable Register Name: PIO_MDDR Address: 0xFFFFF454 (PIOA), 0xFFFFF654 (PIOB), 0xFFFFF854 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi Drive Disable 0: No effect. 1: Disables Multi Drive on the I/O line.
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28.6.20 PIO Multi-driver Status Register Name: PIO_MDSR Address: 0xFFFFF458 (PIOA), 0xFFFFF658 (PIOB), 0xFFFFF858 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi Drive Status 0: The Multi Drive is disabled on the I/O line.
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28.6.21 PIO Pull Up Disable Register Name: PIO_PUDR Address: 0xFFFFF460 (PIOA), 0xFFFFF660 (PIOB), 0xFFFFF860 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Disable 0: No effect. 1: Disables the pull up resistor on the I/O line.
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28.6.22 PIO Pull Up Enable Register Name: PIO_PUER Address: 0xFFFFF464 (PIOA), 0xFFFFF664 (PIOB), 0xFFFFF864 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Enable 0: No effect. 1: Enables the pull up resistor on the I/O line.
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28.6.23 PIO Pull Up Status Register Name: PIO_PUSR Address: 0xFFFFF468 (PIOA), 0xFFFFF668 (PIOB), 0xFFFFF868 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Status 0: Pull Up resistor is enabled on the I/O line.
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28.6.24 PIO Peripheral A Select Register Name: PIO_ASR Address: 0xFFFFF470 (PIOA), 0xFFFFF670 (PIOB), 0xFFFFF870 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral A Select 0: No effect. 1: Assigns the I/O line to the Peripheral A function.
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28.6.25 PIO Peripheral B Select Register Name: PIO_BSR Address: 0xFFFFF474 (PIOA), 0xFFFFF674 (PIOB), 0xFFFFF874 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral B Select 0: No effect. 1: Assigns the I/O line to the peripheral B function.
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28.6.26 PIO Peripheral A B Status Register Name: PIO_ABSR Address: 0xFFFFF478 (PIOA), 0xFFFFF678 (PIOB), 0xFFFFF878 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral A B Status 0: The I/O line is assigned to the Peripheral A.
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28.6.27 PIO Output Write Enable Register Name: PIO_OWER Address: 0xFFFFF4A0 (PIOA), 0xFFFFF6A0 (PIOB), 0xFFFFF8A0 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Enable 0: No effect. 1: Enables writing PIO_ODSR for the I/O line.
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28.6.28 PIO Output Write Disable Register Name: PIO_OWDR Address: 0xFFFFF4A4 (PIOA), 0xFFFFF6A4 (PIOB), 0xFFFFF8A4 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Disable 0: No effect. 1: Disables writing PIO_ODSR for the I/O line.
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28.6.29 PIO Output Write Status Register Name: PIO_OWSR Address: 0xFFFFF4A8 (PIOA), 0xFFFFF6A8 (PIOB), 0xFFFFF8A8 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Status 0: Writing PIO_ODSR does not affect the I/O line.
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29. Serial Peripheral Interface (SPI) 29.1 Overview The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
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29.3 Application Block Diagram Figure 29-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPI Master SPCK SPCK MISO MISO MOSI MOSI NPCS0 NSS Slave 0 SPCK NPCS1 NPCS2 NC NPCS3 MISO Slave 1 MOSI NSS SPCK MISO Slave 2 MOSI NSS 29.4 Signal Description Table 29-1.
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29.5 Product Dependencies 29.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. 29.5.2 Power Management The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SPI clock. 29.5.
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Figure 29-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 6 5 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB MISO (from slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 29-4.
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29.6.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register.
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29.6.3.1 Master Mode Block Diagram Figure 29-5. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TDRE TD SPI_CSR0..
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29.6.3.2 Master Mode Flow Diagram Figure 29-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
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29.6.3.3 Clock Generation The SPI baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255. This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
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The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register.
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Figure 29-8. Peripheral Deselection CSAAT = 0 TDRE NPCS[0..3] CSAAT = 1 DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write SPI_TDR TDRE NPCS[0..3] DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS=A PCS = A Write SPI_TDR TDRE NPCS[0..3] DLYBCT DLYBCT A B A B DLYBCS DLYBCS PCS = B PCS = B Write SPI_TDR 29.6.3.
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When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. When a transfer starts, the data shifted out is the data present in the Shift Register.
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29.7 Serial Peripheral Interface (SPI) User Interface Table 29-3.
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29.7.1 SPI Control Register Name: SPI_CR Address: 0xFFFC8000 (0), 0xFFFCC000 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0: No effect. 1: Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0: No effect. 1: Disables the SPI.
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29.7.2 SPI Mode Register Name: SPI_MR Address: 0xFFFC8004 (0), 0xFFFCC004 (1) Access: Read/Write 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – PCS 7 6 5 4 3 2 1 0 LLB – – MODFDIS – PCSDEC PS MSTR • MSTR: Master/Slave Mode 0: SPI is in Slave mode. 1: SPI is in Master mode. • PS: Peripheral Select 0: Fixed Peripheral Select. 1: Variable Peripheral Select.
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• PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS.
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29.7.3 SPI Receive Data Register Name: SPI_RDR Address: 0xFFFC8008 (0), 0xFFFCC008 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
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29.7.4 SPI Transmit Data Register Name: SPI_TDR Address: 0xFFFC800C (0), 0xFFFCC00C (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
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29.7.
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• TXBUFE: TX Buffer Empty 0: SPI_TCR(1) or SPI_TNCR(1) has a value other than 0. 1: Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0. • NSSR: NSS Rising 0: No rising edge detected on NSS pin since last read. 1: A rising edge occurred on NSS pin since last read. • TXEMPTY: Transmission Registers Empty 0: As soon as data is written in SPI_TDR. 1: SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.
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29.7.6 SPI Interrupt Enable Register Name: SPI_IER Address: 0xFFFC8014 (0), 0xFFFCC014 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0: No effect. 1: Enables the corresponding interrupt.
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29.7.7 SPI Interrupt Disable Register Name: SPI_IDR Address: 0xFFFC8018 (0), 0xFFFCC018 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0: No effect. 1: Disables the corresponding interrupt.
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29.7.8 SPI Interrupt Mask Register Name: SPI_IMR Address: 0xFFFC801C (0), 0xFFFCC01C (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
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29.7.9 SPI Chip Select Register Name: SPI_CSR0... SPI_CSR3 Address: 0xFFFC8030 (0), 0xFFFCC030 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 4 BITS 3 2 1 0 CSAAT – NCPHA CPOL Note: SPI_CSRx must be written even if the user wants to use the defaults. The BITS field will not be updated with the translated value unless the register is written.
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• BITS: Bits Per Transfer (See the note below the SPI_CSR bitmap.) The BITS field determines the number of data bits transferred. Reserved values should not be used.
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• DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers.
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30. Two Wire Interface (TWI) 30.1 Overview The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few.
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30.3 List of Abbreviations Table 30-2. 30.4 Abbreviations Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write Block Diagram Figure 30-1.
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30.5 Application Block Diagram Figure 30-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 30.5.1 I/O Lines Description Table 30-3. 30.6 I/O Lines Description Pin Name Pin Description Type TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output Product Dependencies 30.6.
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30.7 Functional Description 30.7.1 Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 30-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 30-3).  A high-to-low transition on the TWD line while TWCK is high defines the START condition.
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30.8.2 Application Block Diagram Figure 30-5. Master Mode Typical Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 30.8.3 Programming Master Mode The following registers have to be programmed before entering Master mode: 1.
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Figure 30-6. Master Write with One Data Byte STOP Command sent (write in TWI_CR) S TWD DADR W A DATA A P TXCOMP TXRDY Write THR (DATA) Figure 30-7. Master Write with Multiple Data Bytes STOP command performed (by writing in the TWI_CR) TWD S DADR W A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Figure 30-8.
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30.8.5 Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge.
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30.8.6 Internal Address The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 30.8.6.1 7-bit Slave Addressing When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example.
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30.8.6.2 10-bit Slave Addressing For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave Addressing. Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. Program IADRSZ = 1, 2.
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Figure 30-15.
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Figure 30-16.
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Figure 30-17.
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Figure 30-18.
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Figure 30-19.
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Figure 30-20.
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30.9 Multi-master Mode 30.9.1 Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop.
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Figure 30-21. Programmer Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 30-22.
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Figure 30-23.
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30.10 Slave Mode 30.10.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 30.10.2 Application Block Diagram Figure 30-24.
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30.10.4.2 Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 30-26 on page 411. 30.10.4.
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30.10.5.2 Write Operation The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
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30.10.5.4 Clock Synchronization In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded.
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Clock Synchronization in Write Mode The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 30-29 describes the clock synchronization in Read mode. Figure 30-29.
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30.10.5.5 Reversal after a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 30-30 describes the repeated start + reversal from Read to Write mode. Figure 30-30.
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30.10.6 Read Write Flowcharts The flowchart shown in Figure 30-32 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 30-32.
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30.11 Two-wire Interface (TWI) User Interface Table 30-4.
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30.11.1 TWI Control Register Name: TWI_CR Address: 0xFFFAC000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 QUICK 5 SVDIS 4 SVEN 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0: No effect. 1: A frame beginning with a START bit is transmitted according to the features defined in the mode register.
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• SVDIS: TWI Slave Mode Disabled 0: No effect. 1: The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • QUICK: SMBUS Quick Command 0: No effect. 1: If Master mode is enabled, a SMBUS Quick Command is sent. • SWRST: Software Reset 0: No effect. 1: Equivalent to a system reset.
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30.11.
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30.11.3 TWI Slave Mode Register Name: TWI_SMR Address: 0xFFFAC008 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode. SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect.
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30.11.4 TWI Internal Address Register Name: TWI_IADR Address: 0xFFFAC00C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ.
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30.11.5 TWI Clock Waveform Generator Register Name: TWI_CWGR Address: 0xFFFAC010 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV TWI_CWGR is only used in Master mode.
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30.11.6 TWI Status Register Name: TWI_SR Address: 0xFFFAC020 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0: During the length of the current frame.
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If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 30-25 on page 410, Figure 30-28 on page 412, Figure 30-30 on page 414 and Figure 30-31 on page 414. • SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant.
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• ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. • SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0: The clock is not stretched. 1: The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character.
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30.11.
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30.11.
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30.11.
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30.11.
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30.11.
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31. Universal Synchronous Asynchronous Receiver Transmitter (USART) 31.1 Overview The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
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31.3 Application Block Diagram Figure 31-2. Application Block Diagram IrLAP PPP Serial Driver Field Bus Driver EMV Driver IrDA Driver USART 31.4 RS485 Drivers Serial Port Differential Bus Smart Card Slot IrDA Transceivers I/O Lines Description Table 31-1. 31.
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31.5.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode. 31.6 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications.
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31.6.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter.
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Table 31-2. Baud Rate Example (OVER = 0) Source Clock (MHz) Expected Baud Rate (bit/s) Calculation Result CD Actual Baud Rate (bit/s) Error 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.
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The modified architecture is presented below: Figure 31-4. Fractional Baud Rate Generator FP USCLKS CD Modulus Control FP CD MCK MCK/DIV SCK SCK 0 1 Reserved 16-bit Counter 2 3 glitch-free logic 1 0 FIDI >1 SYNC OVER 0 0 Sampling Divider 0 Baud Rate Clock 1 1 SYNC Sampling Clock USCLKS = 3 31.6.1.4 Baud Rate in Synchronous Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR.
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Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 31-4. Table 31-4. Binary and Decimal Values for Fi FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 Fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 Table 31-5 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 31-5.
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After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR).
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Figure 31-7. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY 31.6.3.2 Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line.
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Figure 31-9. Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 31.6.3.3 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start.
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31.6.3.4 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1. Figure 31-11.
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31.6.3.5 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode” on page 443. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd.
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31.6.3.6 Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1.
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Table 31-7. Maximum Timeguard Length Depending on Baud Rate (Continued) Baud Rate (bit/s) Bit Time (µs) Timeguard (ms) 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21 31.6.3.8 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line.
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Table 31-8 gives the maximum time-out period for some standard baud rates. Table 31-8. Maximum Time-out Period Baud Rate (bit/s) Bit Time (µs) Time-out (ms) 600 1 667 109 225 1 200 833 54 613 2 400 417 27 306 4 800 208 13 653 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 56000 18 1 170 57600 17 1 138 200000 5 328 31.6.3.9 Framing Error The receiver is capable of detecting framing errors.
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character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing US_CR with the STPBRK bit at 1.
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31.6.3.12 Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 31-17. Figure 31-17. Connection with a Remote Device for Hardware Handshaking USART Remote Device TXD RXD RXD TXD CTS RTS RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2.
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31.6.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. 31.6.4.
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Figure 31-21. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 31-22. T = 0 Protocol with Parity Error Baud Rate Clock Error I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Bit Time 1 D0 Guard Start Time 2 Bit D1 Repetition 31.6.4.3 Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register.
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31.6.4.7 Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR). 31.6.5 IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication.
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31.6.5.1 IrDA Modulation For baud rates up to and including 115.2 kbit/s, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 31-9. Table 31-9. IrDA Pulse Duration Baud Rate Pulse Duration (3/16) 2.4 kbit/s 78.13 µs 9.6 kbit/s 19.53 µs 19.2 kbit/s 9.77 µs 38.4 kbit/s 4.88 µs 57.6 kbit/s 3.26 µs 115.2 kbit/s 1.63 µs Figure 31-24 shows an example of character transmission. Figure 31-24.
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31.6.5.2 IrDA Baud Rate Table 31-10 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 31-10. 452 IrDA Baud Rate Error Peripheral Clock Baud Rate (bit/s) CD Baud Rate Error Pulse Time (µs) 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.63 32 768 000 115 200 18 1.25% 1.63 40 000 000 115 200 22 1.38% 1.63 3 686 400 57 600 4 0.00% 3.
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31.6.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time.
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Figure 31-27. Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY RTS 31.6.7 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 31.6.7.
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31.6.7.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 31-30. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 31-30. Local Loopback Mode Configuration RXD Receiver 1 Transmitter TXD 31.6.7.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 31-31.
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31.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 31-11.
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31.7.1 USART Control Register Name: US_CR Address: 0xFFFB0000 (0), 0xFFFB4000 (1), 0xFFFB8000 (2) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RTSDIS 18 RTSEN 17 – 16 – 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter.
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• STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect.
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31.7.
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• PAR: Parity Type Value Parity Type 0 0 0 Even parity 0 0 1 Odd parity 0 1 0 Parity forced to 0 (Space) 0 1 1 Parity forced to 1 (Mark) 1 0 x No parity 1 1 x Multidrop mode • NBSTOP: Number of Stop Bits Value Asynchronous (SYNC = 0) Synchronous (SYNC = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits Reserved 1 0 2 stop bits 2 stop bits 1 1 Reserved Reserved • CHMODE: Channel Mode Value Mode Description 0 0 Normal Mode 0 1 Automatic Echo.
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• DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. • MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T= 0.
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31.7.
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31.7.
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31.7.
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31.7.6 USART Channel Status Register Name: US_CSR Address: 0xFFFB0014 (0), 0xFFFB4014 (1), 0xFFFB8014 (2) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CTS 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY • RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled.
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• PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
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31.7.7 USART Receive Holding Register Name: US_RHR Address: 0xFFFB0018 (0), 0xFFFB4018 (1), 0xFFFB8018 (2) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command.
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31.7.8 USART Transmit Holding Register Name: US_THR Address: 0xFFFB001C (0), 0xFFFB401C (1), 0xFFFB801C (2) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
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31.7.
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31.7.10 USART Receiver Time-out Register Name: US_RTOR Address: 0xFFFB0024 (0), 0xFFFB4024 (1), 0xFFFB8024 (2) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO • TO: Time-out Value 0: The Receiver Time-out is disabled. 1–65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period.
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31.7.11 USART Transmitter Timeguard Register Name: US_TTGR Address: 0xFFFB0028 (0), 0xFFFB4028 (1), 0xFFFB8028 (2) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG • TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1–255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period.
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31.7.12 USART FI DI RATIO Register Name: US_FIDI Address: 0xFFFB0040 (0), 0xFFFB4040 (1), 0xFFFB8040 (2) Access: Read/Write Reset Value: 0x174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal.
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31.7.13 USART Number of Errors Register Name: US_NER Address: 0xFFFB0044 (0), 0xFFFB4044 (1), 0xFFFB8044 (2) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
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31.7.14 USART IrDA FILTER Register Name: US_IF Address: 0xFFFB004C (0), 0xFFFB404C (1), 0xFFFB804C (2) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER • IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator.
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32. Synchronous Serial Controller (SSC) 32.1 Overview The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider.
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32.3 Application Block Diagram Figure 32-2. Application Block Diagram OS or RTOS Driver Power Management Interrupt Management Test Management SSC Serial AUDIO 32.4 Time Slot Management Frame Management Line Interface Pin Name List Table 32-1. 32.
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32.6 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts.
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32.6.1 Clock Management The transmitter clock can be generated by:  an external clock received on the TK I/O pad  the receiver clock  the internal clock divider The receiver clock can be generated by:  an external clock received on the RK I/O pad  the transmitter clock  the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad.
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32.6.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR.
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32.6.1.3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR.
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32.6.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See “Start” on page 482. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See “Frame Sync” on page 484.
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32.6.3 Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See “Start” on page 482. The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See “Frame Sync” on page 484. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR.
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Figure 32-10. Transmit Start Mode TK TF (Input) Start = Low Level on TF Start = Falling Edge on TF Start = High Level on TF Start = Rising Edge on TF Start = Level Change on TF Start = Any Edge on TF TD (Output) TD (Output) X BO STTDLY BO X B1 STTDLY BO X TD (Output) B1 STTDLY TD (Output) BO X B1 STTDLY TD (Output) TD (Output) B1 BO X B1 BO B1 STTDLY X B1 BO BO B1 STTDLY Figure 32-11.
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32.6.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform.  Programmable low or high levels during data transfer are supported.  Programmable high levels before the start of data transfers or toggling are also supported.
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32.6.6.1 Compare Functions Length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is defined by FSLEN, but with a maximum value of 16 bits. Comparison is always done by comparing the last bits received with the comparison pattern. Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R).
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Figure 32-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes Start Start PERIOD TF/RF (1) FSLEN TD (If FSDEN = 1) Sync Data Data Data From SSC_THR From SSC_THR Default TD (If FSDEN = 0) RD Default From SSC_TSHR FromDATDEF Sync Data Ignored Default From SSC_THR Data To SSC_RSHR From DATDEF Ignored Data To SSC_RHR To SSC_RHR DATLEN DATLEN STTDLY Sync Data FromDATDEF Data Data From SSC_THR From DATDEF Default Sync Data DATNB Note: 1.
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32.6.9 Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event.
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Figure 32-18. Codec Application Block Diagram Serial Data Clock (SCLK) TK Frame sync (FSYNC) TF CODEC Serial Data Out TD SSC Serial Data In RD RF Serial Data Clock (SCLK) Frame sync (FSYNC) RK First Time Slot Dstart Dend Serial Data Out Serial Data In Figure 32-19.
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32.8 Synchronous Serial Controller (SSC) User Interface Table 32-3.
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32.8.1 SSC Control Register Name: SSC_CR Address: 0xFFFBC000 (0), 0xFFFC0000 (1), 0xFFFC4000 (2) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN • RXEN: Receive Enable 0: No effect. 1: Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0: No effect. 1: Disables Receive.
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32.8.2 SSC Clock Mode Register Name: SSC_CMR Address: 0xFFFBC004 (0), 0xFFFC0004 (1), 0xFFFC4004 (2) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DIV 3 2 DIV • DIV: Clock Divider 0: The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190.
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32.8.
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• START: Receive Start Selection Value Receive Start 0x0 Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
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32.8.4 SSC Receive Frame Mode Register Name: SSC_RFMR Address: 0xFFFBC014 (0), 0xFFFC0014 (1), 0xFFFC4014 (2) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 FSEDGE 23 – 22 21 FSOS 20 19 18 17 16 15 – 14 – 13 – 12 – 11 9 8 7 MSBF 6 – 5 LOOP 4 3 1 0 FSLEN 10 DATNB 2 DATLEN • DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits.
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• FSOS: Receive Frame Sync Output Selection Value Selected Receive Frame Sync Signal RF Pin 0x0 None 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6–0x7 Input-only Reserved Undefined • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
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32.8.
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• START: Transmit Start Selection Value Transmit Start 0x0 Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data.
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32.8.6 SSC Transmit Frame Mode Register Name: SSC_TFMR Address: 0xFFFBC01C (0), 0xFFFC001C (1), 0xFFFC401C (2) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 FSEDGE 23 FSDEN 22 21 FSOS 20 19 18 17 16 15 – 14 – 13 – 12 – 11 9 8 7 MSBF 6 – 5 DATDEF 4 3 1 0 FSLEN 10 DATNB 2 DATLEN • DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits.
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• FSDEN: Frame Sync Data Enable 0: The TD line is driven with the default value during the Transmit Frame Sync signal. 1: SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal. • FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync will generate the interrupt TXSYN (Status Register).
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32.8.7 SSC Receive Holding Register Name: SSC_RHR Address: 0xFFFBC020 (0), 0xFFFC0020 (1), 0xFFFC4020 (2) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.
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32.8.8 SSC Transmit Holding Register Name: SSC_THR Address: 0xFFFBC024 (0), 0xFFFC0024 (1), 0xFFFC4024 (2) Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TDAT 23 22 21 20 TDAT 15 14 13 12 TDAT 7 6 5 4 TDAT • TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.
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32.8.
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32.8.
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32.8.
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32.8.
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32.8.13 SSC Status Register Name: SSC_SR Address: 0xFFFBC040 (0), 0xFFFC0040 (1), 0xFFFC4040 (2) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready 0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1: SSC_THR is empty.
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• RXBUFF: Receive Buffer Full 0: SSC_RCR or SSC_RNCR have a value other than 0. 1: Both SSC_RCR and SSC_RNCR have a value of 0. • CP0: Compare 0 0: A compare 0 has not occurred since the last read of the Status Register. 1: A compare 0 has occurred since the last read of the Status Register. • CP1: Compare 1 0: A compare 1 has not occurred since the last read of the Status Register. 1: A compare 1 has occurred since the last read of the Status Register.
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32.8.14 SSC Interrupt Enable Register Name: SSC_IER Address: 0xFFFBC044 (0), 0xFFFC0044 (1), 0xFFFC4044 (2) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Enable 0: 0: No effect. 1: Enables the Transmit Ready Interrupt.
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• RXBUFF: Receive Buffer Full Interrupt Enable 0: No effect. 1: Enables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Enable 0: No effect. 1: Enables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Enable 0: No effect. 1: Enables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Enables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Enables the Rx Sync Interrupt.
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32.8.15 SSC Interrupt Disable Register Name: SSC_IDR Address: 0xFFFBC048 (0), 0xFFFC0048 (1), 0xFFFC4048 (2) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Disable 0: No effect. 1: Disables the Transmit Ready Interrupt.
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• RXBUFF: Receive Buffer Full Interrupt Disable 0: No effect. 1: Disables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Disable 0: No effect. 1: Disables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Disable 0: No effect. 1: Disables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Disables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Disables the Rx Sync Interrupt.
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32.8.16 SSC Interrupt Mask Register Name: SSC_IMR Address: 0xFFFBC04C (0), 0xFFFC004C (1), 0xFFFC404C (2) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Mask 0: The Transmit Ready Interrupt is disabled. 1: The Transmit Ready Interrupt is enabled.
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• RXBUFF: Receive Buffer Full Interrupt Mask 0: The Receive Buffer Full Interrupt is disabled. 1: The Receive Buffer Full Interrupt is enabled. • CP0: Compare 0 Interrupt Mask 0: The Compare 0 Interrupt is disabled. 1: The Compare 0 Interrupt is enabled. • CP1: Compare 1 Interrupt Mask 0: The Compare 1 Interrupt is disabled. 1: The Compare 1 Interrupt is enabled. • TXSYN: Tx Sync Interrupt Mask 0: The Tx Sync Interrupt is disabled. 1: The Tx Sync Interrupt is enabled.
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33. Timer Counter (TC) 33.1 Overview The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user.
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33.3 Block Diagram Figure 33-1.
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33.5 Product Dependencies 33.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. 33.5.2 Power Management The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock. 33.5.
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Figure 33-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 XC0 = TCLK2 TIOA0 TIOA1 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 33-3.
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33.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 33-4.  The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR.
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33.6.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes:  Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR.  SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger.
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SAM9261 [DATASHEET] Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16 MTIOA MTIOB 1 If RA is not loaded or RB is Loaded Edge Detector ETRGEDG SWTRG Timer/Counter Channel ABETRG BURST CLKI R S OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP R S CLKEN LDRA If RA is Loaded CPCTRG 16-bit Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR TIOA TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK
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33.6.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR).
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SAM9261 [DATASHEET] Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16 TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST TCCLKS Timer/Counter Channel Edge Detector EEVTEDG SWTRG ENETRG CLKI Trig CLK R S OVF WAVSEL RESET 16-bit Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA A
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33.6.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 33-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 33-8. RC Compare cannot be programmed to generate a trigger in this configuration.
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33.6.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 33-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 33-10.
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33.6.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 33-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 33-12.
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33.6.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 33-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 33-14.
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33.6.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined.
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33.7 Timer Counter (TC) User Interface Table 33-4.
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33.7.1 TC Block Control Register Name: TC_BCR Address: 0xFFFA00C0 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – SYNC • SYNC: Synchro Command 0: No effect. 1: Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
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33.7.
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33.7.3 TC Channel Control Register Name: TC_CCRx [x=0..2] Address: 0xFFFA0000 (0)[0], 0xFFFA0040 (0)[1], 0xFFFA0080 (0)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – SWTRG CLKDIS CLKEN • CLKEN: Counter Clock Enable Command 0: No effect. 1: Enables the clock if CLKDIS is not 1.
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33.7.4 TC Channel Mode Register: Capture Mode Name: TC_CMRx [x=0..
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• ETRGEDG: External Trigger Edge Selection Value Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • ABETRG: TIOA or TIOB External Trigger Selection 0: TIOB is used as an external trigger. 1: TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0: RC Compare has no effect on the counter and its clock. 1: RC Compare resets the counter and starts the counter clock. • WAVE 0: Capture Mode is enabled. 1: Capture Mode is disabled (Waveform Mode is enabled).
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33.7.5 TC Channel Mode Register: Waveform Mode Name: TC_CMRx [x=0..2] (WAVE = 1) Address: 0xFFFA0004 (0)[0], 0xFFFA0044 (0)[1], 0xFFFA0084 (0)[2] Access: Read/Write 31 30 29 BSWTRG 23 22 20 14 7 6 CPCDIS CPCSTOP 12 Clock Selected 0 0 0 TIMER_CLOCK1 0 0 1 TIMER_CLOCK2 0 1 0 TIMER_CLOCK3 0 1 1 TIMER_CLOCK4 1 0 0 TIMER_CLOCK5 1 0 1 XC0 1 1 0 XC1 1 1 1 XC2 5 4 BURST • CLKI: Clock Invert 0: Counter is incremented on rising edge of the clock.
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• EEVTEDG: External Event Edge Selection Value Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • EEVT: External Event Selection Value Signal selected as external event TIOB Direction 0 0 TIOB input (1) 0 1 XC0 output 1 0 XC1 output 1 1 XC2 output Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs.
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• ACPC: RC Compare Effect on TIOA Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • AEEVT: External Event Effect on TIOA Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • ASWTRG: Software Trigger Effect on TIOA Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BCPB: RB Compare Effect on TIOB Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BCPC: RC Compare Effect on TIOB Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BE
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• BSWTRG: Software Trigger Effect on TIOB Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle SAM9261 [DATASHEET] Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16 537
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33.7.6 TC Counter Value Register Name: TC_CVx [x=0..2] Address: 0xFFFA0010 (0)[0], 0xFFFA0050 (0)[1], 0xFFFA0090 (0)[2] Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time.
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33.7.7 TC Register A Name: TC_RAx [x=0..2] Address: 0xFFFA0014 (0)[0], 0xFFFA0054 (0)[1], 0xFFFA0094 (0)[2] Access: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RA 7 6 5 4 RA • RA: Register A RA contains the Register A value in real time.
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33.7.8 TC Register B Name: TC_RBx [x=0..2] Address: 0xFFFA0018 (0)[0], 0xFFFA0058 (0)[1], 0xFFFA0098 (0)[2] Access: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RB 7 6 5 4 RB • RB: Register B RB contains the Register B value in real time.
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33.7.9 TC Register C Name: TC_RCx [x=0..2] Address: 0xFFFA001C (0)[0], 0xFFFA005C (0)[1], 0xFFFA009C (0)[2] Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RC 7 6 5 4 RC • RC: Register C RC contains the Register C value in real time.
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33.7.10 TC Status Register Name: TC_SRx [x=0..2] Address: 0xFFFA0020 (0)[0], 0xFFFA0060 (0)[1], 0xFFFA00A0 (0)[2] Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow Status 0: No counter overflow has occurred since the last read of the Status Register.
PAGE 543
• CLKSTA: Clock Enabling Status 0: Clock is disabled. 1: Clock is enabled. • MTIOA: TIOA Mirror 0: TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1: TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0: TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1: TIOB is high.
PAGE 544
33.7.11 TC Interrupt Enable Register Name: TC_IERx [x=0..2] Address: 0xFFFA0024 (0)[0], 0xFFFA0064 (0)[1], 0xFFFA00A4 (0)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0: No effect. 1: Enables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0: No effect.
PAGE 545
33.7.12 TC Interrupt Disable Register Name: TC_IDRx [x=0..2] Address: 0xFFFA0028 (0)[0], 0xFFFA0068 (0)[1], 0xFFFA00A8 (0)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0: No effect. 1: Disables the Counter Overflow Interrupt.
PAGE 546
33.7.13 TC Interrupt Mask Register Name: TC_IMRx [x=0..2] Address: 0xFFFA002C (0)[0], 0xFFFA006C (0)[1], 0xFFFA00AC (0)[2] Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0: The Counter Overflow Interrupt is disabled. 1: The Counter Overflow Interrupt is enabled.
PAGE 547
34. MultiMedia Card Interface (MCI) 34.1 Overview The MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specification V2.2 and the SD Memory Card Specification V1.0. The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead.
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34.3 Block Diagram Figure 34-1. Block Diagram APB Bridge PDC APB MCCK (1) MCI Interface PMC MCK PIO MCCDA (1) MCDA0 (1) MCDA1 (1) MCDA2 (1) MCDA3 (1) Interrupt Control MCI Interrupt Note: 34.4 1. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy. Application Block Diagram Figure 34-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc.
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34.5 Pin Name List Table 34-1. I/O Lines Description Pin Name(2) Pin Description Type(1) Comments MCCDA Command/response I/O/PP/OD CMD of an MMC or SDCard MCCK Clock I/O CLK of an MMC or SD Card MCDA0–MCDA3 Data 0..3 of Slot A I/O/PP DAT0 of an MMC DAT[0..3] of an SD Card Notes: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy. 34.6 Product Dependencies 34.6.
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34.7 Bus Topology Figure 34-3. Multimedia Memory Card Bus Topology 1234567 MMC The MultiMedia Card communication is based on a 7-pin serial bus interface. It has three communication lines and four supply lines. Table 34-2.
PAGE 551
Table 34-3. SD Memory Card Bus Signals Description MCI Pin Name(2) (Slot z) I/O/PP Card detect/ Data line Bit 3 MCDz3 CMD PP Command/response MCCDz 3 VSS1 S Supply voltage ground VSS 4 VDD S Supply voltage VDD 5 CLK I/O Clock MCCK 6 VSS2 S Supply voltage ground VSS 7 DAT[0] I/O/PP Data line Bit 0 MCDz0 8 DAT[1] I/O/PP Data line Bit 1 MCDz1 9 DAT[2] I/O/PP Data line Bit 2 MCDz2 Pin Number Name Type 1 CD/DAT[3] 2 1. 2. Figure 34-6.
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There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock MCI Clock.
PAGE 553
The argument register (MCI_ARGR) contains the argument field of the command. To send a command, the user must perform the following steps:  Fill MCI_ARGR with the command argument.  Set MCI_CMDR (see Table 34-5). The command is sent immediately after writing the command register. The status bit CMDRDY in the Status Register (MCI_SR) is asserted when the command is completed.
PAGE 554
Figure 34-7.
PAGE 555
34.8.2 Data Transfer Operation The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kind of transfers can be selected setting the Transfer Type (TRTYP) field in the MCI_CMDR. These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is set in MCI_MR, then all reads and writes use the PDC facilities. In all cases, the block length (BLKLEN field) must be defined in the mode register MCI_MR.
PAGE 556
Figure 34-8.
PAGE 557
34.8.4 Write Operation In write operation, the MCI Mode Register (MCI_MR) is used to define the padding value when writing non-multiple block size. If the bit PDCPADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used. If set, the bit PDCMODE enables PDC transfer. The following flowchart shows how to write a single block with or without use of PDC facilities (see Figure 34-9).
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Figure 34-9.
PAGE 559
The following flowchart shows how to manage a multiple write block transfer with the PDC (see Figure 34-10). Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register (MCI_IMR). Figure 34-10.
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34.9 SD Card Operations The MultiMedia Card Interface allows processing of SD Memory (Secure Digital Memory Card) Card commands. SD cards are based on the Multi Media Card (MMC) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security features. The physical form factor, pin assignment and data transfer protocol are forward-compatible with the MultiMedia Card with some additions.
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34.10 MultiMedia Card Interface (MCI) User Interface Table 34-6.
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34.10.1 MCI Control Register Name: MCI_CR Address: 0xFFFA8000 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – PWSDIS PWSEN MCIDIS MCIEN • MCIEN: Multi-Media Interface Enable 0: No effect. 1: Enables the Multi-Media Interface if MCDIS is 0. • MCIDIS: Multi-Media Interface Disable 0: No effect.
PAGE 563
34.10.2 MCI Mode Register Name: MCI_MR Address: 0xFFFA8004 Access: Read/write 31 30 – – 23 22 29 28 27 26 25 24 18 17 16 0 0 9 8 BLKLEN 21 20 19 BLKLEN 15 14 13 12 11 PDCMODE PDCPADV – – – 7 6 5 4 10 PWSDIV 3 2 1 0 CLKDIV • CLKDIV: Clock Divider Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) divided by (2*(CLKDIV+1)).
PAGE 564
34.10.3 MCI Data Timeout Register Name: MCI_DTOR Address: 0xFFFA8008 Access: Read/write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – DTOMUL DTOCYC • DTOCYC: Data Timeout Cycle Number Defines a number of Master Clock cycles with DTOMUL.
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34.10.4 MCI SDCard Register Name: MCI_SDCR Address: 0xFFFA800C Access: Read/write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 1 7 6 5 4 3 2 SDCBUS – – – – – 0 SDCSEL • SDCSEL: SDCard Slot Value SDCard Slot 0 0 Slot A is selected.
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34.10.
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34.10.6 MCI Command Register Name: MCI_CMDR Address: 0xFFFA8014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 18 17 – – – 15 14 13 12 11 – – – MAXLAT OPDCMD 6 5 4 3 7 19 TRTYP RSPTYP TRDIR 10 16 TRCMD 9 8 SPCMD 2 1 0 CMDNB This register is write-protected while CMDRDY is 0 in MCI_SR. If an Interrupt command is sent, this register is only writeable by an interrupt response (field SPCMD).
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• MAXLAT: Max Latency for Command to Response 0: 5-cycle max latency 1: 64-cycle max latency • TRCMD: Transfer Command Value Transfer Type 0 0 No data transfer 0 1 Start data transfer 1 0 Stop data transfer 1 1 Reserved • TRDIR: Transfer Direction 0: Write 1: Read • TRTYP: Transfer Type Value Transfer Type 0 0 0 MMC/SDCard Single Block 0 0 1 MMC/SDCard Multiple Block 0 1 0 MMC Stream 0 1 1 Reserved 568 SAM9261 [DATASHEET] Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
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34.10.7 MCI Response Register Name: MCI_RSPR Address: 0xFFFA8020 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RSP 23 22 21 20 RSP 15 14 13 12 RSP 7 6 5 4 RSP • RSP: Response Note: The response register can be read by N accesses at the same MCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response.
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34.10.
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34.10.
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34.10.10 MCI Status Register Name: MCI_SR Address: 0xFFFA8040 Access: Read-only 31 30 29 28 27 26 25 24 UNRE OVRE – – – – – – 23 22 21 20 19 18 17 16 – DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE 15 14 13 12 11 10 9 8 TXBUFE RXBUFF – – – – – – 7 6 5 4 3 2 1 0 ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY • CMDRDY: Command Ready 0: A command is in progress. 1: The last command has been sent. Cleared when writing in the MCI_CMDR.
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0: The MCI is not ready for new data transfer. Cleared at the end of the card response. 1: The MCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a free internal data receive buffer of the card. Refer to the MMC or SD Specification for more details concerning the busy behavior. • ENDRX: End of RX Buffer 0: The Receive Counter Register has not reached 0 since the last write in MCI_RCR or MCI_RNCR.
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• DCRCE: Data CRC Error 0: No error. 1: A CRC16 error has been detected in the last data block. Cleared by reading in the MCI_SR. • DTOE: Data Time-out Error 0: No error. 1: The data time-out set by DTOCYC and DTOMUL in MCI_DTOR has been exceeded. Cleared by reading in the MCI_SR. • OVRE: Overrun 0: No error. 1: At least one 8-bit received data has been lost (not read). Cleared when sending a new data transfer command. • UNRE: Underrun 0: No error.
PAGE 575
34.10.
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• UNRE: UnderRun Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.
PAGE 577
34.10.
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• UNRE: UnderRun Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.
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34.10.
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• UNRE: UnderRun Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
PAGE 581
35. USB Host Port (UHP) 35.1 Overview The USB Host Port (UHP) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as USB v2.0 Full-speed and Low-speed protocols. The USB Host Port integrates a root hub and transceivers on downstream ports. It provides several high-speed half-duplex serial communication ports at a baud rate of 12 Mbit/s. Up to 127 USB devices (printer, camera, mouse, keyboard, disk, etc.
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35.3 Block Diagram Figure 35-1. Block Diagram HCI Slave Block AHB Slave OHCI Registers OHCI Root Hub Registers List Processor Block Control ED & TD Regsisters Root Hub and Host SIE Embedded USB v2.0 Full-speed Transceiver PORT S/M USB transceiver DP DM PORT S/M USB transceiver DP DM AHB HCI Master Block Data FIFO 64 x 8 Master uhp_int MCK UHPCK Access to the USB host operational registers is achieved through the AHB bus slave interface.
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35.4 Product Dependencies 35.4.1 I/O Lines DPs and DMs are not controlled by any PIO controllers. The embedded USB physical transceivers are controlled by the USB host controller. 35.4.2 Power Management The USB host controller requires a 48 MHz clock. This clock must be generated by a PLL with a correct accuracy of ± 0.25%.
PAGE 584
35.5 Functional Description Please refer to the Open Host Controller Interface Specification for USB Release 1.0.a. 35.5.1 Host Controller Interface There are two communication channels between the Host Controller and the Host Controller Driver. The first channel uses a set of operational registers located on the USB Host Controller. The Host Controller is the target for all communications on this channel. The operational registers contain control, status and list pointer registers.
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35.5.2 Host Controller Driver Figure 35-3. USB Host Drivers User Application User Space Kernel Drivers Mini Driver Class Driver Class Driver HUB Driver USB Driver Host Controller Driver Hardware Host Controller Hardware USB Handling is done through several layers as follows: 35.6  Host controller hardware and serial engine: Transmits and receives USB data on the bus.  Host controller driver: Drives the Host controller hardware and handles the USB protocol.
PAGE 586
36. USB Device Port (UDP) 36.1 Overview The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral.
PAGE 587
36.3 Block Diagram Figure 36-1. Block Diagram Atmel Bridge MCK APB to MCU Bus UDPCK USB Device txoen U s e r I n t e r f a c e udp_int external_resume W r a p p e r Dual Port RAM FIFO W r a p p e r eopn Serial Interface Engine 12 MHz txd rxdm Embedded USB Transceiver DP DM rxd SIE rxdp Suspend/Resume Logic Master Clock Domain Recovered 12 MHz Domain Access to the UDP is via the APB bus interface.
PAGE 588
36.4.2 Power Management The USB device peripheral requires a 48 MHz clock. This clock must be generated by a PLL with an accuracy of ± 0.25%. Thus, the USB device receives two clocks from the Power Management Controller (PMC): the master clock, MCK, used to drive the peripheral user interface, and the UDPCK, used to interface with the bus USB signals (recovered 12 MHz domain).
PAGE 589
36.6 Functional Description 36.6.1 USB V2.0 Full-speed Introduction The USB V2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB device through a set of communication flows. Figure 36-3. Example of USB V2.0 Full-speed Communication Control USB Host V2.
PAGE 590
36.6.1.3 USB Transfer Event Definitions As indicated below, transfers are sequential events carried out on the USB bus. Table 36-3.
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36.6.2 Handling Transactions with USB V2.0 Device Peripheral 36.6.2.1 Setup Transaction Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device. These requests are then handled by the USB device and may require more arguments.
PAGE 592
36.6.2.2 Data IN Transaction Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. Data IN transactions in isochronous transfer must be done using endpoints with pingpong attributes. 36.6.2.3 Using Endpoints Without Ping-pong Attributes To perform a Data IN transaction using a non ping-pong endpoint: 1.
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36.6.2.4 Using Endpoints With Ping-pong Attribute The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This also allows handling the maximum bandwidth defined in the USB specification during bulk transfer. To be able to guarantee a constant or the maximum bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the USB device. Thus two banks of memory are used.
PAGE 594
Figure 36-8.
PAGE 595
36.6.2.5 Data OUT Transaction Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-pong attributes. 36.6.2.6 Data OUT Transaction Without Ping-pong Attributes To perform a Data OUT transaction, using a non ping-pong endpoint: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint.
PAGE 596
36.6.2.7 Using Endpoints With Ping-pong Attributes During isochronous transfer, using an endpoint with ping-pong attributes is obligatory. To be able to guarantee a constant bandwidth, the microcontroller must read the previous data payload sent by the host, while the current data payload is received by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 36-10.
PAGE 597
Figure 36-11.
PAGE 598
Figure 36-12. Stall Handshake (Data IN Transfer) USB Bus Packets Data IN PID Stall PID Cleared by Firmware FORCESTALL Set by Firmware Interrupt Pending Cleared by Firmware STALLSENT Set by USB Device Figure 36-13. Stall Handshake (Data OUT Transfer) USB Bus Packets Data OUT PID Data OUT Stall PID Set by Firmware FORCESTALL Interrupt Pending STALLSENT Cleared by Firmware Set by USB Device 36.6.2.
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36.6.3 Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0. Figure 36-14.
PAGE 600
36.6.3.2 Entering Attached State When no device is connected, the USB DP and DM signals are tied to GND by 15 KΩ pull-down resistors integrated in the hub downstream ports. When a device is attached to a hub downstream port, the device connects a 1.5 KΩ pull-up resistor on DP. The USB bus line goes into IDLE state, DP is pulled up by the device 1.5 KΩ resistor to 3.3V and DM is pulled down by the 15 KΩ resistor of the host.
PAGE 601
Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. Switching off MCK for the UDP peripheral must be one of the last operations after writing to the UDP_TXVC and acknowledging the RXSUSP. 36.6.3.7 Receiving a Host Resume In suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks are disabled (however the pullup shall not be removed).
PAGE 602
36.7 USB Device Port (UDP) User Interface WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXVC register. Table 36-4.
PAGE 603
36.7.1 UDP Frame Number Register Name: UDP_FRM_NUM Address: 0xFFFA4000 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 FRM_OK 16 FRM_ERR 15 – 14 – 13 – 12 – 11 – 10 9 FRM_NUM 8 7 6 5 4 3 2 1 0 FRM_NUM • FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame.
PAGE 604
36.7.2 UDP Global State Register Name: UDP_GLB_STAT Address: 0xFFFA4004 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 – 6 – 5 – 4 – 3 – 2 – 1 CONFG 0 FADDEN This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0. • FADDEN: Function Address Enable Read: 0: Device is not in address state.
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36.7.3 UDP Function Address Register Name: UDP_FADDR Address: 0xFFFA4008 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – FEN 7 – 6 5 4 3 FADD 2 1 0 • FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence.
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36.7.
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36.7.
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36.7.
PAGE 609
Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register UDP_IMR is enabled.
PAGE 610
36.7.
PAGE 611
• RXRSM: UDP Resume Interrupt Status 0: No UDP Resume Interrupt pending. 1: UDP Resume Interrupt has been raised. The USB device sets this bit when a UDP resume signal is detected at its port. After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ICR. • SOFINT: Start of Frame Interrupt Status 0: No Start of Frame Interrupt pending. 1: Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected.
PAGE 612
36.7.8 UDP Interrupt Clear Register Name: UDP_ICR Address: 0xFFFA4020 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12 ENDBUSRES 11 SOFINT 10 – 9 RXRSM 8 RXSUSP 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • RXSUSP: Clear UDP Suspend Interrupt 0: No effect. 1: Clears UDP Suspend Interrupt. • RXRSM: Clear UDP Resume Interrupt 0: No effect. 1: Clears UDP Resume Interrupt.
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36.7.
PAGE 614
36.7.10 UDP Endpoint Control and Status Register Name: UDP_CSRx [x = 0..
PAGE 615
• RX_DATA_BK0: Receive Data Bank 0 This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0: Notify USB peripheral device that data have been read in the FIFO's Bank 0. 1: To leave the read value unchanged. Read (Set by the USB peripheral): 0: No data packet has been received in the FIFO's Bank 0. 1: A data packet has been received, it has been stored in the FIFO's Bank 0.
PAGE 616
ISOERROR: A CRC error has been detected in an isochronous transfer. Read: 0: No error in the previous isochronous transfer. 1: CRC error has been detected, data available in the FIFO are corrupted. Write: 0: Resets the ISOERROR flag, clears the interrupt. 1: No effect. • TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device. This flag is set by the USB device firmware. Read: 0: There is no data to send. 1: The data is waiting to be sent upon reception of token IN.
PAGE 617
• RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes) This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0: Notifies USB device that data have been read in the FIFO’s Bank 1. 1: To leave the read value unchanged. Read (Set by the USB peripheral): 0: No data packet has been received in the FIFO's Bank 1. 1: A data packet has been received, it has been stored in FIFO's Bank 1.
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• EPEDS: Endpoint Enable Disable Read: 0: Endpoint disabled. 1: Endpoint enabled. Write: 0: Disables endpoint. 1: Enables endpoint. Control endpoints are always enabled. Reading or writing this field has no effect on control endpoints. Note: After reset, all endpoints are configured as control endpoints (zero). • RXBYTECNT[10:0]: Number of Bytes Available in the FIFO Read-only When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller.
PAGE 619
36.7.11 UDP FIFO Data Register Name: UDP_FDRx [x = 0..5] Address: 0xFFFA404C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 6 5 4 3 2 1 0 FIFO_DATA • FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_CSRx is the number of bytes to be read from the FIFO (sent by the host).
PAGE 620
36.7.12 UDP Transceiver Control Register Name: UDP_TXVC Address: 0xFFFA4074 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – TXVDIS 7 – 6 – 5 – 4 – 3 – 2 – 1 0 – – WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXVC register.
PAGE 621
37. LCD Controller (LCDC) 37.1 Overview The LCD Controller (LCDC) consists of logic for transferring LCD image data from an external display buffer to an LCD module with integrated common and segment drivers. The LCD Controller supports single and double scan monochrome and color passive STN LCD modules and single scan active TFT LCD modules. On monochrome STN displays, up to 16 gray shades are supported using a time-based dithering algorithm and Frame Rate Control (FRC) method.
PAGE 622
37.2 Block Diagram Figure 37-1.
PAGE 623
37.3 I/O Lines Description Table 37-1. I/O Lines Description Name Description Type LCDCC Contrast control signal Output LCDHSYNC Line synchronous signal (STN) or Horizontal synchronous signal (TFT) Output LCDDOTCK LCD clock signal (STN/TFT) Output LCDVSYNC Frame synchronous signal (STN) or Vertical synchronization signal (TFT) Output LCDDEN Data enable signal Output LCDD[23:0] LCD Data Bus output Output 37.4 Product Dependencies 37.4.
PAGE 624
37.5.1.3 Channel-U This block stores the base address and the number of words transferred for this channel (frame in single scan mode and Upper Panel in dual scan mode) since the beginning of the frame. It also generates the end of frame signal. It has two pointers, the base address and the number of words to transfer. When the module receives a new_frame signal, it reloads the number of words to transfer pointer with the size of the frame/panel.
PAGE 625
Figure 37-2. Datapath Structure Input Interface FIFO Serializer Configuration IF Palette Control Interface Dithering Output Shifter Output Interface This module transforms the data read from the memory into a format according to the LCD module used. It has four different interfaces: the input interface, the output interface, the configuration interface and the control interface.  The input interface connects the datapath with the DMA controller.
PAGE 626
Table 37-2. Datapath Parameters Configuration DISTYPE SCAN IFWIDTH initial_latency cycles_per_data TFT Single Not applicable 9 1 STN Mono Single 4 13 4 STN Mono Single 8 17 8 STN Mono Dual 8 17 8 STN Mono Dual 16 25 16 STN Color Single 4 11 2 STN Color Single 8 12 3 STN Color Dual 8 14 4 STN Color Dual 16 15 6 37.5.2.3 FIFO The FIFO block buffers the input data read by the DMA module.
PAGE 627
37.5.2.4 Serializer This block serializes the data read from memory. It reads words from the FIFO and outputs pixels (1 bit, 2 bits, 4 bits, 8 bits, 16 bits or 24 bits wide) depending on the format specified in the PIXELSIZE field of the LCDCON2 register. It also adapts the memory-ordering format. Both big-endian and little-endian formats are supported. They are configured in the MEMOR field of the LCDCON2 register.
PAGE 628
37.5.2.5 Palette This block is used to generate the pixel gray or color information in palletized configurations. The different modes with the palletized/non-palletized configuration can be found in Table 37-5. In these modes, 1, 2, 4 or 8 input bits index an entry in the lookup table. The corresponding entry in the lookup table contains the color or gray shade information for the pixel. Table 37-5.
PAGE 629
37.5.2.6 Dithering The dithering block is used to generate the shades of gray or color when the LCD Controller is used with an STN LCD Module. It uses a time-based dithering algorithm and Frame Rate Control method. The Frame Rate Control varies the duty cycle for which a given pixel is turned on, giving the display an appearance of multiple shades.
PAGE 630
Table 37-8. Dithering Algorithm for Monochrome Mode Frame Number Pattern Pixel a Pixel b Pixel c Pixel d N 1010 ON OFF ON OFF N+1 0101 OFF ON OFF ON N+2 1010 ON OFF ON OFF N+3 0101 OFF ON OFF ON N+4 1111 ON ON ON ON N+5 1010 ON OFF ON OFF N+6 0101 OFF ON OFF ON N+7 1010 ON OFF ON OFF ... ... ... ... ... ... Consider now color display mode and two pixels p0 and p1 with the horizontal coordinates 4*n+0, and 4*n+1.
PAGE 631
Table 37-9. Dithering Algorithm for Color Mode (Continued) Frame Signal Shadow Level Bit used Dithering Pattern 4-bit LCDD 8-bit LCDD Output N+2 green_data_1 1010 3 0110 LCDD[3] LCDD[3] g1 N+2 blue_data_1 1010 2 0110 LCDD[2] LCDD[2] B1 … … … … … … … … Note: Ri = red pixel component ON. Gi = green pixel component ON. Bi = blue pixel component ON. ri = red pixel component OFF. gi = green pixel component OFF. bi = blue pixel component OFF. 37.5.2.
PAGE 632
Table 37-10. Minimum LCDDOTCK Period in LCDC Core Clock Cycles (Continued) Configuration DISTYPE SCAN IFWIDTH LCDDOTCK Period STN Color Single 4 2 STN Color Single 8 2 STN Color Dual 8 4 STN Color Dual 16 6 The LCDDEN signal indicates valid data in the LCD Interface. After each horizontal line of data has been shifted into the LCD, the LCDHSYNC is asserted to cause the line to be displayed on the panel.
PAGE 633
There are two other parameters to configure in this module, the HOZVAL and the LINEVAL fields of the LCDFRMCFG:  HOZVAL configures the number of active LCDDOTCK cycles in each line. The number of active cycles in each line is equal to (HOZVAL+1) cycles. The minimum value of this parameter is 1.  LINEVAL configures the number of active lines per frame. This number is equal to (LINEVAL+1) lines. The minimum value of this parameter is 1.
PAGE 634
Figure 37-4. TFT Panel Timing, CLKMOD = 0, VPW = 2, VBP = 2, VFP = 1 Frame Period (VPW+1) Lines LCDVSYNC Vertical Fron t Porch = VFP Lines Vertical Back Porch = VBP Lines VHDLY+1 LCDHSYNC LCDDEN LCDDOTCK LCDD Line Period VHDLY+1 HPW+1 HOZVAL+1 HBP+1 HFP+2 LCDVSYNC LCDHSYNC LCDDEN LCDDOTCK LCDD 1 PCLK Figure 37-5.
PAGE 635
In monochrome mode, Horizontal_display_size is equal to the number of horizontal pixels. The number_data_lines is equal to the number of bits of the interface in single scan mode; number_data_lines is equal to half the bits of the interface in dual scan mode. In color mode, Horizontal_display_size equals three times the number of horizontal pixels.
PAGE 636
37.5.3 LCD Interface The LCD Controller interfaces with the LCD Module through the LCD Interface (Table 37-11 on page 640). The Controller supports the following interface configurations: 24-bit TFT single scan, 16-bit STN Dual Scan Mono (Color), 8-bit STN Dual (Single) Scan Mono (Color), 4-bit single scan Mono (Color). A 4-bit single scan STN display uses 4 parallel data lines to shift data to successive single horizontal lines one at a time until the entire frame has been shifted and transferred.
PAGE 637
Figure 37-7. Single Scan Monochrome and Color 4-bit Panel Timing (First Line Expanded View) LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDD [3] P0 P4 LCDD [2] P1 P5 LCDD [1] P2 P6 LCDD [0] P3 P7 LCDD [3] R0 G1 LCDD [2] G0 B1 LCDD [1] B0 R2 LCDD [0] R1 G2 LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK Figure 37-8.
PAGE 638
Figure 37-9.
PAGE 639
Figure 37-10.
PAGE 640
Table 37-11.
PAGE 641
37.6 Interrupts The LCD Controller generates six different IRQs. All the IRQs are synchronized with the internal LCD Core Clock. The IRQs are:  DMA Memory error IRQ. Generated when the DMA receives an error response from an AHB slave while it is doing a data transfer.  FIFO underflow IRQ. Generated when the Serializer tries to read a word from the FIFO when the FIFO is empty.  FIFO overwrite IRQ. Generated when the DMA Controller tries to write a word in the FIFO while the FIFO is full.
PAGE 642
̶ LCDFRMCFG register: program the dimensions of the LCD module used. ̶ LCDFIFO register: To program it, use the formula in section “FIFO” on page 626. ̶  DP1_2 to DP6_7 registers: they are only used for STN displays. They contain the dithering patterns used to generate gray shades or colors in these modules. They are loaded with recommended patterns at reset, so it is not necessary to write anything on them.
PAGE 643
37.9 Register Configuration Guide Program the PIO Controller to enable LCD signals. Enable the LCD controller clock in the Power Management Controller. PMC_SCER = 1 << 17;//LCDC HCLK = HCK1 37.9.1 STN Mode Example STN color(R,G,B) 320*240, 8-bit single scan, 70 frames/sec, Master clock = 60 MHz Data rate: 320*240*70*3/8 = 2.016 MHz HOZVAL= ((3*320)/8) - 1 LINEVAL= 240 -1 CLKVAL = (60 MHz/ (2*2.
PAGE 644
37.10 LCD Controller (LCDC) User Interface Table 37-12.
PAGE 645
37.10.1 DMA Base Address Register 1 Name: DMABADDR1 Address: 0x00600000 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 0 0 BADDR-U 23 22 21 20 BADDR-U 15 14 13 12 BADDR-U 7 6 5 4 BADDR-U • BADDR-U Base Address for the upper panel in dual scan mode. Base Address for the complete frame in single scan mode.
PAGE 646
37.10.2 DMA Base Address Register 2 Name: DMABADDR2 Address: 0x00600004 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BADDR-L 23 22 21 20 BADDR-L 15 14 13 12 BADDR-L 7 6 5 4 BADDR-L • BADDR-L Base Address for the lower panel in dual scan mode only.
PAGE 647
37.10.3 DMA Frame Pointer Register 1 Name: DMAFRMPT1 Address: 0x00600008 Access: Read-only 31 – 23 – 15 30 – 22 29 – 21 14 13 7 6 5 28 – 20 27 – 19 FRMPT-U 12 11 FRMPT-U 4 3 FRMPT-U 26 – 18 25 – 17 24 – 16 10 9 8 2 1 0 • FRMPT-U Current value of frame pointer for the upper panel in dual scan mode. Current value of frame pointer for the complete frame in single scan mode. Down count from FRMSIZE to 0.
PAGE 648
37.10.4 DMA Frame Pointer Register 2 Name: DMAFRMPT2 Address: 0x0060000C Access: Read-only 31 – 23 15 30 – 22 29 – 21 28 – 20 14 13 12 7 6 5 4 27 – 19 FRMPT-L 11 FRMPT-L 3 FRMPT-L 26 – 18 25 – 17 24 – 16 10 9 8 2 1 0 • FRMPT-L Current value of frame pointer for the Lower panel in dual scan mode only. Down count from FRMSIZE to 0. Note: This register is read-only and contains the current value of the frame pointer (number of words to the end of the frame).
PAGE 649
37.10.5 DMA Frame Address Register 1 Name: DMAFRMADD1 Address: 0x00600010 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FRMADD-U 23 22 21 20 FRMADD-U 15 14 13 12 FRMADD-U 7 6 5 4 FRMADD-U • FRMADD-U Current value of frame address for the upper panel in dual scan mode. Current value of frame address for the complete frame in single scan.
PAGE 650
37.10.6 DMA Frame Address Register 2 Name: DMAFRMADD2 Address: 0x00600014 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FRMADD-L 23 22 21 20 FRMADD-L 15 14 13 12 FRMADD-L 7 6 5 4 FRMADD-L • FRMADD-L Current value of frame address for the lower panel in single scan mode only. Note: This register is read-only and contains the current value of the last DMA transaction in the bus for the panel.
PAGE 651
37.10.7 DMA Frame Configuration Register Name: DMAFRMCFG Address: 0x00600018 Access: Read/Write 31 – 23 – 15 30 29 28 22 21 20 14 13 12 7 6 5 4 27 BRSTLN 19 FRMSIZE 11 FRMSIZE 3 FRMSIZE 26 25 24 18 17 16 10 9 8 2 1 0 • FRMSIZE: Frame Size In single scan mode, this is the frame size in words. In dual scan mode, this is the size of each panel.
PAGE 652
37.10.8 DMA Control Register Name: DMACON Address: 0x0060001C Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 - 27 – 19 – 11 – 3 - 26 – 18 – 10 – 2 DMABUSY • DMAEN: DMA Enable 0: DMA is disabled. 1: DMA is enabled. • DMARST: DMA Reset (Write-only) 0: No effect. 1: Reset DMA module. DMA Module should be reset only when disabled and in idle state. • DMABUSY: DMA Busy 0: DMA module is idle. 1: DMA module is busy (doing a transaction on the AHB bus).
PAGE 653
37.10.9 LCD Control Register 1 Name: LCDCON1 Address: 0x00600800 Access: Read/Write, except LINECNT: Read-only 31 30 29 28 27 26 25 24 18 CLKVAL 10 – 2 – 17 16 9 – 1 – 8 – 0 BYPASS LINECNT 23 15 7 – 22 LINECNT 14 CLKVAL 6 – 21 20 19 13 12 5 – 4 – 11 – 3 – • BYPASS: Bypass LCDDOTCK divider 0: The divider is not bypassed. LCDDOTCK frequency defined by the CLKVAL field. 1: The LCDDOTCK divider is bypassed. LCDDOTCK frequency is equal to the LCDC Clock frequency.
PAGE 654
37.10.
PAGE 655
• INVVD: LCDD polarity 0: Normal 1: Inverted • INVFRAME: LCDVSYNC polarity 0: Normal (active high) 1: Inverted (active low) • INVLINE: LCDHSYNC polarity 0: Normal (active high) 1: Inverted (active low) • INVCLK: LCDDOTCK polarity 0: Normal (LCDD fetched at LCDDOTCK falling edge) 1: Inverted (LCDD fetched at LCDDOTCK rising edge) • INVDVAL: LCDDEN polarity 0: Normal (active high) 1: Inverted (active low) • CLKMOD: LCDDOTCK mode 0: LCDDOTCK only active during active display period 1: LCDDOTCK always active •
PAGE 656
37.10.11 LCD Timing Configuration Register 1 Name: LCDTIM1 Address: 0x00600808 Access: Read/Write 31 – 23 – 15 30 – 22 – 14 29 – 21 28 – 20 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 VHDLY 19 VPW 13 12 VBP 7 6 5 4 VFP • VFP: Vertical Front Porch In TFT mode, these bits equal the number of idle lines at the end of the frame. In STN mode, these bits should be set to 0. • VBP: Vertical Back Porch In TFT mode, these bits equal the number of idle lines at the beginning of the frame.
PAGE 657
37.10.12 LCD Timing Configuration Register 2 Name: LCDTIM2 Address: 0x0060080C Access: Read/Write 31 30 29 28 27 26 25 24 13 20 – 12 19 – 11 18 – 10 17 – 9 16 – 8 5 4 3 2 1 0 HFP 23 15 – 7 22 HFP 14 – 6 21 HPW HBP • HBP: Horizontal Back Porch Number of idle LCDDOTCK cycles at the beginning of the line. Idle period is (HBP+1) LCDDOTCK cycles. • HPW: Horizontal synchronization pulse width Width of the LCDHSYNC pulse, given in LCDDOTCK cycles. Width is (HPW+1) LCDDOTCK cycles.
PAGE 658
37.10.13 LCD Frame Configuration Register Name: LCDFRMCFG Address: 0x00600810 Access: Read/Write 31 30 29 28 27 26 25 24 19 – 11 – 3 18 – 10 17 – 9 LINEVAL 1 16 – 8 HOZVAL 23 22 HOZVAL 14 – 6 15 – 7 21 13 – 5 20 – 12 – 4 2 0 LINEVAL • LINEVAL: Vertical size of LCD module LINEVAL = (Vertical display size) - 1 In dual scan mode, vertical display size refers to the size of each panel.
PAGE 659
37.10.14 LCD FIFO Register Name: LCDFIFO Address: 0x00600814 Access: Read/Write 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 3 2 1 0 FIFOTH FIFOTH • FIFOTH: FIFO Threshold Must be programmed with: FIFOTH = 512 - (2 x DMA_BURST_LENGTH + 3) where: • 512 is the effective size of the FIFO. It is the total FIFO memory size in single scan mode and half that size in dual scan mode.
PAGE 660
37.10.
PAGE 661
37.10.
PAGE 662
37.10.
PAGE 663
37.10.
PAGE 664
37.10.
PAGE 665
37.10.
PAGE 666
37.10.
PAGE 667
37.10.
PAGE 668
37.10.23 Power Control Register Name: PWRCON Address: 0x0060083C Access: Read/Write 31 LCD_BUSY 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 GUARD_TIME 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 LCD_PWR • LCD_PWR: LCD module power control 0: lcd_pwr signal is low, other lcd_* signals are low. 0->1: lcd_* signals activated, lcd_pwr is set high with the delay of GUARD_TIME frame periods. 1: lcd_pwr signal is high, other lcd_* signals are active.
PAGE 669
37.10.24 Contrast Control Register Name: CONTRAST_CTR Address: 0x00600840 Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 ENA 26 – 18 – 10 – 2 POL 25 – 17 – 9 – 1 24 – 16 – 8 – 0 PS • PS This 2-bit value selects the configuration of a counter prescaler. The meaning of each combination is as follows: Value Description 0 0 The counter advances at a rate of fCOUNTER = fLCDC_CLOCK.
PAGE 670
37.10.25 Contrast Value Register Name: CONTRAST_VAL Address: 0x00600844 Access: Read/Write 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 CVAL • CVAL PWM compare value. Used to adjust the analog value obtained after an external filter to control the contrast of the display.
PAGE 671
37.10.
PAGE 672
37.10.
PAGE 673
37.10.
PAGE 674
37.10.
PAGE 675
37.10.
PAGE 676
38. Electrical Characteristics 38.1 Absolute Maximum Ratings Table 38-1. Absolute Maximum Ratings* Storage Temperature...................................... -60°C to +150°C *NOTICE: Voltage on Input Pins with Respect to Ground ......................................-0.3V to +4.0V Maximum Operating Voltage (VDDCORE and VDDBU)...................................................1.5V Maximum Operating Voltage (VDDOSC, VDDPLL, VDDIOM and VDDIOP)....................4.
PAGE 677
Table 38-2. DC Characteristics (Continued) Symbol Parameter Conditions IO Output Current ISC 38.3 Min Typ Max Unit PA0–PA31, PB0–PB31, PC0–PC31, SHDN – – 8 mA On VDDCORE = 1.2V, MCK = 0 Hz, excluding POR, All inputs driven TMS, TDI, TCK, NRST = 1 TA = 25°C – 245 – TA = 85°C – – 3000 On VDDBU = 1.2V, Logic cells consumption, excluding POR, All inputs driven WKUP = 0 TA = 25°C – 1.13 – TA = 85°C – – 9.
PAGE 678
These figures represent the power consumption measured on the power supplies. Table 38-3. Power Consumption for Different Modes Mode Conditions Consumption VDDCORE = 1.08V Full speed ARM Core clock is 188 MHz TA = 85°C MCK is 94 MHz VDDCORE = 1.2V Dhrystone running in Icache TA = 85°C onto AMP2 VDDCORE = 1.2V 52.7 58 VDDCORE = 1.08V Idle (1) TA = 85°C ARM core in idle state, waiting on interrupt VDDCORE = 1.2V Processor clock disabled TA = 85°C onto AMP2 VDDCORE = 1.2V 12.0 14.
PAGE 679
38.4 Clock Characteristics 38.4.1 Processor Clock Characteristics Table 38-5. Processor Clock Waveform Parameters Symbol Parameter 1/(tCPPCK) Processor Clock Frequency Conditions VDDCORE = 1.08V TA = 85°C Min Max Unit – 188 MHz Min Max Unit – 94 MHz 38.4.2 Master Clock Characteristics Table 38-6. Master Clock Waveform Parameters Symbol Parameter 1/(tCPMCK) Master Clock Frequency Conditions VDDCORE = 1.08V TA = 85°C 38.4.3 XIN Clock Characteristics Table 38-7.
PAGE 680
38.5 Crystal Oscillator Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C and worst case of power supply, unless otherwise specified. 38.5.1 32 kHz Oscillator Characteristics Table 38-8. 32 kHz Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit 1/(tCP32KHz) Crystal Oscillator Frequency – – 32.768 – kHz CCRYSTAL32 Crystal Load Capacitance Crystal @ 32.768 kHz 6 – 12.5 pF – 4 – CCRYSTAL32 = 12.
PAGE 681
38.5.3 Main Oscillator Characteristics Table 38-10. Main Oscillator Characteristics Symbol Parameter 1/(tCPMAIN) Crystal Oscillator Frequency CCRYSTAL Crystal Load Capacitance Conditions CCRYSTAL = 12.5 pF(5) CLEXT(6) External Load Capacitance (5) CCRYSTAL = 15 pF (5) CCRYSTAL = 17.5 pF Duty Cycle Min Typ Max Unit 3 16 20 MHz 12.5 15 17.5 pF – 15 – – 18 – – 22 – 40 50 60 pF % VDDPLL = 3 to 3.
PAGE 682
38.5.4 Crystal Characteristics Table 38-11. Symbol ESR Crystal Characteristics Parameter Conditions Min Typ Max Fundamental @ 3 MHz – – 200 Fundamental @ 8 MHz – – 100 Fundamental @ 16 MHz – – 80 Fundamental @ 20 MHz – – 50 Equivalent Series Resistor Rs Unit Ω Cm Motional Capacitance – – – 8 fF CSHUNT Shunt Capacitance – – – 7 pF Min Typ Max Unit CKGR_PLL.OUT = 00 80 – 200 CKGR_PLL.
PAGE 683
38.6 USB Transceiver Characteristics 38.6.1 Electrical Characteristics Table 38-13. Symbol USB Transceiver Electrical Parameters Parameter Conditions Min Typ Max Unit Input Levels VIL Low Level – – – 0.8 V VIH High Level – 2.0 – – V VDI Differential Input Sensitivity |(D+) - (D-)| 0.2 – – V VCM Differential Input Common Mode Range – 0.8 – 2.5 V CIN Transceiver capacitance Capacitance to ground on each line – – 9.
PAGE 684
38.8 EBI Timings These timings are given for  Worst case process  TA = 85°C  VDDCORE = Min  1.8V VDDIOM supply: range 1.65–1.95 V, 30 pF load capacitance  3.3V VDDIOM supply: range 3.0–3.6 V, 50 pF load capacitance Table 38-15. SMC Read Signals with Hold Settings Min 1.8V VDDIOM Supply Symbol Parameter 1.08V VDDCORE Supply 1.2V VDDCORE Supply 3.3V VDDIOM Supply 1.08V VDDCORE Supply 1.2V VDDCORE Supply Unit NRD Controlled (READ_MODE = 1) SMC1 Data Setup before NRD High 13.5 10.
PAGE 685
Table 38-15. SMC Read Signals with Hold Settings (Continued) Min 1.8V VDDIOM Supply Symbol 1.08V VDDCORE Supply Parameter 3.3V VDDIOM Supply 1.2V VDDCORE Supply 1.08V VDDCORE Supply 1.2V VDDCORE Supply Unit NCS Controlled (READ_MODE = 0) SMC10 Data Setup before NCS High 16.5 12.7 13.6 10.6 ns SMC11 Data Hold after NCS High 0 0 0 0 ns SMC12 NCS High to NBS0/A0 Change(1) ncs rd hold length * tCPMCK - 2.6 ncs rd hold length * tCPMCK - 1.8 ncs rd hold length * tCPMCK - 2.
PAGE 686
Table 38-17. SMC Write Signals with Hold Settings Min 1.8V VDDIOM Supply Symbol 1.08V VDDCORE Supply Parameter 1.2V VDDCORE Supply 3.3V VDDIOM Supply 1.08V VDDCORE Supply 1.2V VDDCORE Supply Unit NWE Controlled (WRITE_MODE = 1) SMC23 Data Out Valid before NWE High (NWE pulse length) * tCPMCK 3.8 (NWE pulse length) * tCPMCK 2.9 (NWE pulse length) * tCPMCK 2.7 (NWE pulse length) * tCPMCK 2.1 ns SMC24 Data Out Valid after NWE High(1) NWE hold length * tCPMCK - 5.
PAGE 687
Table 38-18. SMC Write Signals with No Hold Settings (NWE Controlled Only) Min 1.8V VDDIOM Supply 3.3V VDDIOM Supply 1.08V VDDCORE Supply 1.2V VDDCORE Supply 1.08V VDDCORE Supply 1.2V VDDCORE Supply Unit NWE Rising to A2–A25 Valid 3.2 3.2 2.6 2.6 ns SMC38 NWE Rising to NBS0/A0 Valid 3.2 3.2 2.6 2.6 ns SMC39 NWE Rising to NBS1 Change 3.1 3.1 2.5 2.5 ns SMC40 NWE Rising to A1/NBS2 Change 3.3 3.3 2.7 2.7 ns SMC41 NWE Rising to NBS3 Change 3.1 3.1 2.5 2.
PAGE 688
Figure 38-5. SMC Signals for NRD and NWR Controlled Access SMC37 SMC7 SMC7 SMC31 A2-A25 SMC38 SMC39 SMC40 SMC41 SMC3 SMC4 SMC5 SMC6 SMC3 SMC4 SMC5 SMC6 SMC25 SMC26 SMC29 SMC30 A0/A1/NBS[3:0] SMC42 SMC8 SMC32 NCS SMC8 NRD SMC9 SMC19 SMC9 SMC20 SMC43 SMC44 SMC1 SMC23 SMC2 SMC24 D0 - D31 SMC45 SMC33 NWR 38.9 SDRAMC Timings The timings that follow are given for a 10 pF load on SDCK and 50 pF on the databus. Table 38-19.
PAGE 689
Table 38-20. SDRAM Signals (Continued) Min Symbol Parameter 1.8V Supply 3.3V Supply Unit SDRAMC15 CAS Low before SDCK Rising Edge tCPSDCK/2 - 0.4 tCPSDCK/2 - 0.2 ns SDRAMC16 CAS High after SDCK Rising Edge tCPSDCK/2 - 0.3 tCPSDCK/2 - 0.3 ns SDRAMC17 DQM Change before SDCK Rising Edge tCPSDCK/2 - 3.4 tCPSDCK/2 - 3.3 ns SDRAMC18 DQM Change after SDCK Rising Edge tCPSDCK/2 - 0.5 tCPSDCK/2 - 0.5 ns SDRAMC19 D0–D15 in Setup before SDCK Rising Edge 1.4 1.
PAGE 690
Figure 38-6.
PAGE 691
38.10 Peripheral Timings 38.10.1 SPI 38.10.1.1 Maximum SPI Frequency The following formulas give maximum SPI frequency in Master read and write modes and in Slave read and write modes. Master Write Mode The SPI only sends data to a slave device such as an LCD, for example. The limit is given by SPI2 (or SPI5) timing. Since it gives a maximum frequency above the maximum pad speed, the maximum SPI frequency is the one from the pad.
PAGE 692
Figure 38-7. MISO Capture in Master Mode 0 < delay < SPI0 or SPI3 SPCK (generated by the master) MISO Bit N (slave answer) Bit N+1 MISO cannot be provided before the edge tp Common sampling point Device sampling point Safe margin, always > 0 Extended tp Internal shift register Bit N Figure 38-8. SPI Master mode with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0) SPCK SPI0 SPI1 MISO SPI2 MOSI Figure 38-9.
PAGE 693
Figure 38-10. SPI Slave mode with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA= 0) SPCK SPI6 MISO SPI7 SPI8 MOSI Figure 38-11. SPI Slave mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1) SPCK SPI9 MISO SPI10 SPI11 MOSI Table 38-22. Symbol SPI Timings Parameter Conditions Min Max Unit Master Mode SPI0 MISO Setup time before SPCK rises 14.2 + 0.5 * tCPMCK – ns SPI1 MISO Hold time after SPCK rises -3.5 - 0.5 * tCPMCK – ns SPI2 SPCK rising to MOSI 0.
PAGE 694
38.10.2 MCI The PDC interface block controls all data routing between the external data bus, internal MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/SD module (inner system) and the application (user programming). These timings are given for a 25 pF load, corresponding to one MMC/SD Card. Figure 38-12.
PAGE 695
38.10.3 UDP and UHP Switching Characteristics Figure 38-13. USB Data Signal Timing Diagram Rise Time Fall Time 90% VCRS 10% Differential Data Lines 10% tr tf REXT = 27 ohms fosc = 6 MHz/750 kHz Buffer Table 38-24. USB Data Signal Rise and Fall Time Characteristics (Low Speed) Symbol Parameter Conditions tr Transition Rise Time tf trfm Table 38-25.
PAGE 696
39. Mechanical Characteristics 39.1 Package Drawings Figure 39-1. 217-ball LFBGA Package Drawing Table 39-1. Soldering Information (Substrate Level) Ball Land 0.43 mm ± 0.05 Solder Mask Opening 0.30 mm ± 0.05 Table 39-2. Device and 217-ball LFBGA Package Maximum Weight 450 Table 39-3. mg 217-ball LFBGA Package Characteristics Moisture Sensitivity Level Table 39-4.
PAGE 697
39.2 Soldering Profile Table 39-5 gives the recommended soldering profile from J-STD-20. Table 39-5. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/sec. max. Preheat Temperature 175°C ±25°C 180 sec. max. Temperature Maintained Above 217°C 60 sec. to 150 sec. Time within 5°C of Actual Peak Temperature 20 sec. to 40 sec. Peak Temperature Range 260 +0 °C Ramp-down Rate 6°C/sec. max. Time 25°C to Peak Temperature 8 min. max.
PAGE 698
40. Marking All devices are marked with the Atmel logo and the ordering code.
PAGE 699
41. Ordering Information Table 41-1.
PAGE 700
42. Errata 42.1 SAM9261 Errata - Revision A Parts Refer to Section 40. “Marking” on page 698. 42.1.1 Main Oscillator 42.1.1.1 Main Oscillator: Spurious Malfunction of Main Oscillator The main oscillator can exhibit spurious malfunction as exhibited by the duty-cycle not performing according to specification, missing main clock periods, or in the worst case, no main clock at all. The behavior does not alter over time.
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42.1.3.2 Boot ROM: Watchdog Disable When SAM9261 boots on internal ROM (BMS =1) the watchdog timer is disabled by software. Because the watchdog mode register is a “write once”, the system, designed to boot on an SPI DataFlash, cannot reuse the watchdog functionality. Problem Fix/Workaround If the watchdog feature is mandatory for the application, the system must boot on external memory connected on CS0 (BMS = 0). 42.1.3.
PAGE 702
42.1.5.2 LCD: Periodic bad pixels LCD periodic bad pixels is due to mis-aligned DMA base address in frame buffer. LCD DMA performs bursts to read memory. The LCD DMA bursts must not cross the 1-Kbyte AMBA boundary. Problem Fix/Workaround The LCD DMA burst size in 32-bit words is programmed by BRSTLN field in DMAFRMCFG register. The LCD DMA Base Address is programmed in DMABADDR1 register. The LCD DMA Base Address must be programmed with a value aligned onto LCD DMA burst size, e.g.
PAGE 703
42.1.6.4 MCI: STOP during a WRITE_MULTIPLE_BLOCK command The WRITE_MULTIPLE_BLOCK with a transfer size (PDC) not a multiple of the block length is not stopped by the STOP command. Problem Fix/Workaround Choose an appropriate size for the block length. 42.1.7 NTRST 42.1.7.1 NTRST: Device does not boot correctly due to powerup sequencing issue The NTRST signal is powered by VDDIOP power supply (3.3V) and the ARM processor is powered by VDDCORE power supply (1.2V).
PAGE 704
extern void soft_user_reset(void); void sysc_handler(void){ //check if interrupt comes from RSTC if( (*AT91C_RSTC_RSR & AT91C_RSTC_URSTS ) == AT91C_RSTC_URSTS){ soft_user_reset(); //never reached while(1); } }  Assembly code is mandatory for the following sequence as we need to pipeline ARM instructions. The assembler routine: AREA TEST, CODE INCLUDE AT91SAM9xxx.
PAGE 705
42.1.9 SDRAM Controller 42.1.9.1 SDRAM: SDCLK Clock active after reset After a reset the SDRAM clock is always active leading in over consumption in the pad. Problem Fix/Workaround The following sequence allows to stop the SDRAM clock. 1. Set the bit LPCB to 01 (Self-refresh) in the SDRAMC Low Power Register. 2. Write 0 in the SDRAMC Mode Register and perform a dummy write in sdram to complete. 42.1.9.
PAGE 706
42.1.10.4 SPI: Chip Select and fixed mode In FIXED Mode, if a transfer is performed through a PDC on a Chip Select different from the Chip Select 0, the output spi_size sampled by the PDC will depend on the field SPI_CSR0.BITS, whatever the selected Chip Select is. For example if SPI_CSR0 is configured for a 10-bit transfer whereas the SPI_CSR1 is configured for an 8-bit transfer, when a transfer is performed in Fixed mode through the PDC on Chip Select 1, the transfer is considered as a halfword transfer.
PAGE 707
42.1.11 Serial Synchronous Controller (SSC) 42.1.11.1 SSC: Transmitter Limitations in Slave Mode If TK is programmed as input and TF is programmed as output and requested to be set to low/high during data emission, the Frame Synchro is generated one bit clock period after the data start, one data bit is lost. This problem does not exist when generating periodic synchro. Problem Fix/Workaround The data need to be delayed for one bit clock period with an external assembly.
PAGE 708
None. 42.1.12 Shutdown Controller (SHDWC) 42.1.12.1 SHDWC: Boundary Scan Mode Outputs the 32 kHz clock In boundary scan mode, the SHDN pin outputs the 32 kHz clock. Problem/Fix Workaround There is only one way to disable the 32 kHz clock on the SHDN pin. In boundary scan mode, connect TST and JTAGSEL pins to VDDBU and set the SHDN pin to low level. 42.1.12.2 SHDWC: Bad Behavior of Shutdown Pin SHDN signal may be driven to Low level voltage during device power-on.
PAGE 709
42.1.15.2 TWI: Disabling Does not Operate Correctly Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset. Problem Fix/Workaround The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts must be disabled before disabling the TWI. 42.1.15.
PAGE 710
than the minimum safe delay required above. If not, a software wait loop after RXSETUP clear may be added at minimum cost 42.1.17 UHP 42.1.17.1 UHP: Non-ISO IN transfers Conditions: Consider the following sequence: 1. The Host controller issues an IN token. 2. The Device provides the IN data in a short packet. 3. The Host controller writes the received data to the system memory. 4.
PAGE 711
42.1.18 USART 42.1.18.1 USART: CTS signal in Hardware Handshake When Hardware Handshaking is used and if CTS goes low near the end of the starting bit of the transmitter, a character is lost. Problem Fix/Workaround CTS must not go low during a time slot comprised between 2 Master Clock periods before the rising edge of the starting bit and 16 Master Clock periods after the rising edge of the starting bit. 42.1.18.2 USART: RTS unexpected behavior 1.
PAGE 712
42.2 SAM9261 Errata - Revision B Parts Refer to Section 40. “Marking” on page 698. 42.2.1 Main Oscillator 42.2.1.1 Main Oscillator: Spurious Malfunction of Main Oscillator The main oscillator can exhibit spurious malfunction as exhibited by the duty-cycle not performing according to specification, missing main clock periods, or in the worst case, no main clock at all. The behavior does not alter over time.
PAGE 713
None. 42.2.3.2 Boot ROM: UDP Pad Pull-up Enable When SAM9261 boots on internal ROM (BMS = 1), the UDP pad pull-up is enabled by software. This can lead to an enumeration error. Problem Fix/Workaround Disable UDP pad pull-up at the beginning of the boot program (ex: at91bootstrap). 42.2.3.3 Boot ROM: Code Size Limitation for DataFlash and Serial Flash Boot The maximum downloadable code size, from DataFlash and Serial Flash, is limted to 64 Kbytes.
PAGE 714
For a 16-word burst, the LCD DMA Base Address must start on a 16-word offset: 0x0, 0x40, 0x80 or 0xc0. BRSTLN = 3 For a 4-word burst, the LCD DMA Base Address offset must start on a 4-word offset: 0x0, 0x10, ..., 0xf0. 42.2.5.3 LCD: 24-bit Packed Mode LCD DMA Base Address and LCD DMA burst size must be selected with care in 24-bit packed mode. A 32-bit word contains some bits of a pixel and some bits of the following. If LCD DMA Base Address is not aligned with a pixel start, the colors will be modified.
PAGE 715
During the powerup sequence, if VDDIOP power supply is not established whereas the VDDCORE Power On Reset output is released, the NTRST signal is not correctly asserted. This leads to a bad reset of the Embedded Trace Macrocell (ETM9). The ARM processor then enters debug state and the device does not boot correctly. Problem Fix/Workaround 1. Connect NTRST pin to NRST pin to ensure that a correct powering sequence takes place in all cases. 2. Connect NTRST to GND if no debug capabilities are required. 42.
PAGE 716
AREA TEST, CODE INCLUDE AT91SAM9xxx.inc EXPORT soft_user_reset soft_user_reset ;disable IRQs MRS r0, CPSR ORR r0, r0, #0x80 MSR CPSR_c, r0 ;change refresh rate to block all data accesses LDR r0, =AT91C_SDRAMC_TR LDR r1, =1 STR r1, [r0] ;prepare power down command LDR r0, =AT91C_SDRAMC_LPR LDR r1, =2 ;prepare proc_reset and periph_reset LDR r2, =AT91C_RSTC_RCR LDR r3, =0xA5000005 ;perform power down command STR r1, [r0] ;perform proc_reset and periph_reset (in the ARM pipeline) STR r3, [r2] END 42.2.
PAGE 717
Mobile SDRAM initialization must be performed in internal SRAM. 42.2.10 Serial Peripheral Interface (SPI) 42.2.10.1 SPI: Pulse Generation on SPCK In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as follows: ̶ The Baudrate is odd and different from 1. ̶ The Polarity is set to 1. ̶ The Phase is set to 0. Problem Fix/Workaround Do not use this configuration. 42.2.10.2 SPI: Bad PDC behavior when CSAAT = 1 and SCBR = 1 If the SPI2 is programmed with SPI_CSRx.
PAGE 718
42.2.10.7 SPI: Software Reset Must be Written Twice If a software reset (SWRST in the SPI Control Register) is performed, the SPI may not work properly (the clock is enabled before the chip select). Problem Fix/Workaround The field SPI_CR.SWRST needs to be written twice to be correctly set. 42.2.10.8 SPI: Bad Serial Clock Generation on 2nd Chip Select Bad Serial clock generation on the 2nd chip select when SPI_CSRx.SCBR = 1, SPI_CSRx.CPOL = 1 and SPI_CSRx.NCPHA = 0.
PAGE 719
42.2.11.2 SSC: Periodic Transmission Limitations in Master Mode If the Least Significant Bit is sent first (MSBF = 0) the first TAG during the frame synchro is not sent. Problem Fix/Workaround None. 42.2.11.
PAGE 720
For example, the modification of the Chip Select 0 (CS0) parameters, while fetching the code from a memory connected on this CS0, may lead to unpredictable behavior. Problem Fix/Workaround The code used to modify the parameters of an SMC Chip Select can be executed from the internal RAM or from a memory connected to another Chip Select 42.2.14 System Controller (SYSC) 42.2.14.
PAGE 721
42.2.15.6 TWI: STOP not generated If the sequence described as follows occurs: 1. WRITE 1 or more bytes at a given address. 2. Send a STOP. 3. Wait for TXCOMP flag. 4. READ (or WRITE) 1 or more bytes at the same address. then STOP is not generated. The line will show: DADR BYTE 1, ..., BYTE n, NO STOP generated, BYTE 1, ..., BYTE n. Problem Fix/Workaround Insert a delay of one TWI clock period before step 4 in the sequence above. 42.2.16 UDP 42.2.16.
PAGE 722
3. While there is an underrun condition, if the Host controller is in the process of bit-stuffing, it causes the Host controller to hang. Consequence: After the failure condition, the Host controller stops sending the SOF. This causes the connected device to go into suspend state. Problem Fix/Workaround This problem can be avoided if the system can guarantee that no buffer underrun occurs during the transfer. 42.2.17.
PAGE 723
43. Revision History In the tables that follow, the most recent version of the document appears first. The initials “rfo” indicate changes requested by product experts, or made during proof reading as part of the approval process. Table 43-1. Date Revision History - SAM9261 Datasheet Revision 6082O Comments General formatting and editorial changes throughout Several instances of “AT91SAM9261” changed to “SAM9261” Throughout, instances of “32768 Hz” and “32,768 Hz” changed to “32.
PAGE 724
Table 43-1. Date Revision History - SAM9261 Datasheet Revision 6082O Comments Section 12. “Boot Program” (cont’d) Section 12.10.3 “USB Device Port”: deleted reference to “Windows XP” Section 12.11 “Hardware and Software Constraints”: added note “Boot ROM does not support high capacity SDCards.” Section 13. “Reset Controller (RSTC)” Added Section 13.2 “Embedded Characteristics” Section 14. “Real-time Timer (RTT)” Added Section 14.2 “Embedded Characteristics” Section 15.
PAGE 725
Table 43-1. Date Revision History - SAM9261 Datasheet Revision 6082O Comments Section 27. “Debug Unit (DBGU)” Added Section 27.2 “Embedded Characteristics” Table 27-2 “Register Mapping”: - added reset value 0x00181800 for DBGU_SR - added reset value 0x019703A0 for DBGU_CIDR Section 28. “Peripheral Input/Output Controller (PIO)” Figure 28-3 ”I/O Line Control Logic”: redimensioned to display PIO_IDR[31] at bottom of diagram Section 30. “Two Wire Interface (TWI)” Added Section 30.
PAGE 726
Table 43-1. Revision History - SAM9261 Datasheet Revision 6082O Date Comments Section 38. “Electrical Characteristics” (cont’d) Section 38.7 “Core Power Supply POR Characteristics”: transferred power sequence requirements and powerup sequence content to Section 4.
PAGE 727
Change Request Ref. Doc. Rev. Date 6062M 15-Mar-09 Comments Section 7.1.2.1 “BMS = 1, Boot on Embedded ROM”, updated Section 12. “Boot Program”, updated. Section 41. “Ordering Information”, 5424/rfo updated with ordering information for chip revision B. Errata: Section 42.2 “SAM9261 Errata - Revision B Parts”, added to errata. Section 42.1.8 “Reset Controller (RSTC)” 6082 Section 42.1.8.1 “RSTC: Reset During SDRAM Accesses”, added to Rev A parts errata. Section 42.2.
PAGE 728
Doc. Rev. Date 6062L 08-Jan-09 Comments Change Request Ref. Errata: Section 42.1.1 “Main Oscillator” 5960 Section 42.1.1.1 “Main Oscillator: Spurious Malfunction of Main Oscillator”, added to errata. Section 42.1.3 “Boot ROM” 6002 Section 42.1.3.4 “Boot ROM: UDP Pad Pull-up Enable”, added to errata Section 42.1.13 “Static Memory Controller (SMC)” 5642 Section 42.1.13.1 “SMC: Chip Select Parameters Modification”, added to errata. Section 42.1.10 “Serial Peripheral Interface (SPI)” 5956 Section 42.
PAGE 729
Change Request Ref. Doc. Rev. Date 6062K 27-Aug-08 Comments (Continued) LCDC: Table 37-1 “I/O Lines Description”, updated description of LCDDEN. 3587 Section 37.5.1.3 “Channel-U”, Removed equations for STN Monochrome mode and STN Color mode. Updated definitions. Table 37-4 “Big Endian Memory Organization”, Inverted Pixel 1bpp row values to go from 0 to 31. 4268 Section 37.10.23 “Power Control Register”, LCD_PWR bit description, changed all occurences of “pin” to “signal”. Section 37.10.
PAGE 730
Doc. Rev. Date 6062K 27-Aug-08 Comments (Continued) Change Request Ref. RSTC: Figure 13-4 ”Genera Reset State”, updated 4215 Section 13.4.4.1 “General Reset”, extensive update to this section. 4250 Section 13.4.3 “BMS Sampling” and Figure 13-3 ”BMS Sampling” added to datasheet 4372 Section 13.4.4.4 “Software Reset”, PERRST must be used with PROCRST, except for deug purposes. 5436 SHDWC: Table 16-2 “Register Mapping” SHDW_MR reset changed to 0x0000_0303. 5727 SHDW_SR offset value is 0x08.
PAGE 731
Change Request Ref. Doc. Rev. Date 6062K 27-Aug-08 Comments (Continued) UDP: Table 36-2 “USB Communication Flow” changed the value in the cell on the “interrupt line of the “Supported Endpoint Size” column. 3476 Control endpoints are not effected by the ”EPEDS: Endpoint Enable Disable” bit field in the UDP_CSR register. 4063 Updated “write 1 =....” in ”RX_DATA_BK0: Receive Data Bank 0” bit field of UDP_CSR register. 4099 Updated “write 0 =....
PAGE 732
Doc. Rev. Date 6062K 27-Aug-08 Comments (Continued) Change Request Ref. Revision History: Doc. Rev., ”6062H”, Change Request Ref.,”4241”, removed : “PA30 - PA31 power supplies are VDDIOM.” Doc. Rev. 6062J Doc. Rev. 6062I Date 20-Mar-08 Date 06-Feb-08 5333 Comments Change Request Ref. Section 30.
PAGE 733
Doc. Rev. 6062H Date 13-Nov-07 Change Request Ref. Comments Overview: Table 9-4, “Multiplexing on PIO Controller C,” on page 33, 5042 PCO - PC7 power supplies are VDDIOP not VDDIOM. Section 7.1.2 “Boot Strategies”, removed sentence pertaining to “remap” 5027 Section 7.1.2.2 “BMS = 0, Boot on External Memory”, “NANDFlash Boot“ added to list. rfo Section 4.1 “Power Supplies”, startup voltage slope requirements for VDDCORE and VDDBU added.
PAGE 734
Doc. Rev. 6062H Date 13-Nov-07 Comments (Continued) Change Request Ref. Errata: The following have been added. Section 42.1.3.1 “Boot ROM: Only DataFlash Boot Is Functional” rfo Section 42.1.11.1 “SSC: Transmitter Limitations in Slave Mode” Section 42.1.11.3 “SSC: Last RK Clock Cycle when RK Outputs a Clock During Data Transfer”, 4770 Section 42.1.11.4 “SSC: First RK Clock Cycle when RK Outputs a Clock During Data Transfer” Section 42.1.9.2 “SDRAM: JEDEC Standard Compatibility” 4218 Section 42.1.
PAGE 735
Doc. Rev. 6062G 22-Feb-07 Change Request Ref Comments (Continued) 2704 TC: Added information on compare register B and waveform generation in Section 33.6.12 “External Event/Trigger Conditions” on page 527. Added Note (1) to Register Bit Description “EEVT: External Event Selection” on page 535 in “TC Channel Mode Register: Waveform Mode” on page 534 to further clarify. Added Figure 33-2, “Clock Chaining Selection,” on page 517 to demonstrate clock chaining.
PAGE 736
Doc. Rev. 6062E 736 Date 29-Sep-06 Comments Change Request Reference Changed pin name for ball D9 to SHDN in Table 4-1, “AT91SAM9261 Pinout for 217-ball LFBGA Package (1),” on page 10. 3068 Updated peripheral mnemonics in Figure 8-1, “AT91SAM9261 Memory Mapping,” on page 16. 3067 Updated information on shutdown pin in Section 6.5 ”Shutdown Logic Pins” on page 12. 3147 Added note to Table 10-1, “Peripheral Identifiers,” on page 29. 3503 Boot Program: In Section 13.
PAGE 737
Doc. Rev. 6062D Date 14-Apr-06 Change Request Reference Comments Updated information on JTAGSEL in Section 3-1 ”Signal Description by Peripheral” on page 5 and in Section 6.1 ”JTAG Port Pins” on page 11. 2946 Reformatted Section 8. ”Memories” on page 16. Inserted new Figure 8-1, “AT91SAM9261 Memory Mapping,” on page 16 to show full product memory mapping. 2475 Inserted new Section 8.1.2 ”Boot Strategies” on page 20 to replace Boot ROM section.
PAGE 738
Doc. Rev. 6062D Date 14-Apr-06 Comments (Continued) Change Request Reference TC: Section 33.5.12 ”External Event/Trigger Conditions” on page 496 new text as follows: “....(EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs.” Added note (1) to EEVT bit description in Section 33.6.5 ”TC Channel Mode Register: Waveform Mode” on page 504. 2704 MCI: Specified reset condition for DCRCE and DTOE bits in Section 34.10.
PAGE 739
Doc. Rev. 6062D Date 14-Apr-06 Change Request Reference Comments (Continued) Errata: Added: Section “All devices are marked with the Atmel logo and the ordering code.” on page 1. Section 42.1.3.3 “Boot ROM: Temperature Range” on page 701 Section 42.1.6.2 “MCI: Data Timeout Error Flag” on page 702 Section 42.1.6.3 “MCI: STREAM command not supported” on page 702 Section 42.1.6.4 “MCI: STOP during a WRITE_MULTIPLE_BLOCK command” on page 703 Section 42.1.10.
PAGE 740
Doc. Rev. 6062B 740 Date 14-Oct-05 Comments Change Request Reference Changed SPI pin names in Figure 2-1, “AT91SAM9261 Block Diagram,” on page 4, Table 3-1, “Signal Description by Peripheral,” on page 5, Table 10-1, “Multiplexing on PIO Controller A,” on page 30, Table 10-2, “Multiplexing on PIO Controller B,” on page 31 and Table 10-3, “Multiplexing on PIO Controller C,” on page 32.
PAGE 741
Doc. Rev. 6062B Date 14-Oct-05 Change Request Reference Comments (Continued) LCDC: Added information on PMC_SCER register in Section 37.4.2 ”Power Management” on page 561. 05-443 Updated RPULLUP values in Table 38-2, “DC Characteristics,” on page 611. Review Corrected backup consumption value in Table 38-3, “Power Consumption for Different Modes(1),” on page 613. 05-332 Removed data on USB Transceiver Switching Characteristics at low speed in Section 38.
PAGE 742
Table of Contents Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 743
9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.14 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static Memory Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface. . . . .
PAGE 744
14.3 14.4 14.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Real-time Timer (RTT) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 15. Periodic Interval Timer (PIT) . . . . . . . . . . . . . . . . . .
PAGE 745
20.12 Slow Clock Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 20.13 Asynchronous Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 20.14 Static Memory Controller (SMC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 21. SDRAM Controller (SDRAMC) . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 746
27. Debug Unit (DBGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 27.1 27.2 27.3 27.4 27.5 27.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Block Diagram . . . . . . . . . . . . . . .
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32.5 32.6 32.7 32.8 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 SSC Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 Synchronous Serial Controller (SSC) User Interface . . . . . . . .
PAGE 748
37.9 Register Configuration Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 37.10 LCD Controller (LCDC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 38. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 38.1 38.2 38.3 38.4 38.5 38.6 38.7 38.8 38.9 38.10 Absolute Maximum Ratings. . . .
PAGE 749
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