Datasheet

624
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
41.4.10 Two-wire Interface (TWI)
41.4.10.1 TWI: Clock Divider
The value of CLDIV x 2
CKDIV
must be less than or equal to 8191, the value of CHDIV x 2
CKDIV
must be less than or equal
to 8191⋅
Problem Fix/Workaround
None.
41.4.10.2 TWI: Disabling Does not Operate Correctly
Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1.
Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset.
Problem Fix/Workaround
The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts must be disabled before
disabling the TWI.
41.4.10.3 TWI: NACK Status Bit Lost
During a master frame, if TWI_SR is read between the Non Acknowledge condition detection and the TXCOMP bit rising
in the TWI_SR, the NACK bit is not set.
Problem Fix/Workaround
The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as long as transmission is not
completed.
TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of the TWI_SR.
41.4.10.4 TWI: Possible Receive Holding Register Corruption
When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the TWI_RHR is corrupted
at the end of the first subsequent transmit data byte. Neither RXRDY nor OVERRUN status bits are set if this occurs.
Problem Fix/Workaround
The user must be sure that received data is read before transmitting any new data.