Datasheet

48
7679H–CAN–08/08
AT90CAN32/64/128
If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set, Timer/Counter2
will run during sleep. The device can wake up from either Timer Overflow or Output Compare
event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in
TIMSK2, and the global interrupt enable bit in SREG is set.
If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is recommended
instead of Power-save mode because the contents of the registers in the asynchronous timer
should be considered undefined after wake-up in Power-save mode if AS2 is 0.
This sleep mode basically halts all clocks except clk
ASY
, allowing operation only of asynchronous
modules, including Timer/Counter2 if clocked asynchronously.
6.5 Standby Mode
When the SM2..0 bits are 110 and an External Crystal/Resonator clock option is selected, the
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down
with the exception that the Oscillator is kept running. From Standby mode, the device wakes up
in 6 clock cycles.
Notes: 1. Only recommended with external crystal or resonator selected as clock source.
2. If AS2 bit in ASSR is set.
3. Only INT3:0 or level interrupt INT7:4.
6.6 Minimizing Power Consumption
There are several issues to consider when trying to minimize the power consumption in an AVR
controlled system. In general, sleep modes should be used as much as possible, and the sleep
mode should be selected so that as few as possible of the device’s functions are operating. All
functions not needed should be disabled. In particular, the following modules may need special
consideration when trying to achieve the lowest possible power consumption.
6.6.1 Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-
abled before entering any sleep mode. When the ADC is turned off and on again, the next
conversion will be an extended conversion. Refer to “Analog to Digital Converter - ADC” on page
273 for details on ADC operation.
Table 6-2. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains Oscillators Wake-up Sources
Sleep
Mode
clk
CPU
clk
FLASH
clk
IO
clk
ADC
clk
ASY
Main
Clock
Source
Enabled
Timer
Osc.
Enabled
INT7:0
TWI
Address
Match
Timer
2
SPM/
EEPROM
Ready
ADC
Other
I/O
Idle X X X X X
(2)
XXXXXX
ADC Noise
Reduction
XX X X
(2)
X
(3)
XX
(2)
XX
Power-
down
X
(3)
X
Power-
save
X
(2)
X
(2)
X
(3)
XX
(2)
Standby
(1)
XX
(3)
X