Datasheet

37
7679H–CAN–08/08
AT90CAN32/64/128
5. System Clock
5.1 Clock Systems and their Distribution
Figure 5-1 presents the principal clock systems in the AVR and their distribution. All of the clocks
need not be active at a given time. In order to reduce power consumption, the clocks to unused
modules can be halted by using different sleep modes, as described in “Power Management and
Sleep Modes” on page 46. The clock systems are detailed below.
Figure 5-1. Clock Distribution
5.1.1 CPU Clock – clk
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
5.1.2 I/O Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, CAN,
USART. The I/O clock is also used by the External Interrupt module, but note that some external
interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the
I/O clock is halted. Also note that address recognition in the TWI module is carried out asynchro-
nously when clk
I/O
is halted, enabling TWI address reception in all sleep modes.
5.1.3 Flash Clock – clk
FLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
General I/O
Modules
CAN
Controller
CPU Core RAM
clk
I/O
clk
ASY
AVR Clock
Control Unit
clk
CPU
Flash and
EEPROM
clk
FLASH
Source clock
Watchdog Timer
Watchdog
Oscillator
Reset Logic
Prescaler
Clock
Multiplexer
Multiplexer
CKOUT Fuse
CLKO
Watchdog clock
Calibrated RC
Oscillator
Timer/Counter2
Oscillator
External Clock
Crystal
Oscillator
Low-frequency
Crystal Oscillator
External Clock
ADC
clk
ADC
Asynchronous
Timer/Counter2
Timer/Counter2
TOSC2
XTAL2TOSC1 XTAL1