Datasheet

349
7679H–CAN–08/08
AT90CAN32/64/128
Figure 25-7. Serial Programming and Verify
(1)
Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
XTAL1 pin.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
≥ 12 MHz
High: > 2 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
≥ 12 MHz
25.7.2 Pin Mapping
25.7.3 Parameters
The Flash parameters are given in Table 25-11 on page 341 and the EEPROM parameters in
Table 25-12 on page 341.
25.8 SPI Serial Programming
When writing serial data to the AT90CAN32/64/128, data is clocked on the rising edge of SCK.
When reading data from the AT90CAN32/64/128, data is clocked on the falling edge of SCK.
To program and verify the AT90CAN32/64/128 in the serial programming mode, the following
sequence is recommended (See four byte instruction formats in Table 25-15):
VCC
+2.7 - +5.5V
GND
XTAL1
PB1
RESET
PDO
PE1
PE0
PDI
SCK
AVCC
+2.7 - +5.5V
Table 25-13. Pin Mapping Serial Programming
Symbol Pins I/O Description
MOSI (PDI) PE0 I Serial Data in
MISO (PDO) PE1 O Serial Data out
SCK PB1 I Serial Clock