Datasheet

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Table Of Contents

1. Description
- 1.1 Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128
- 1.2 Part Description
- 1.3 Disclaimer
- 1.4 Block Diagram
- 1.5 Pin Configurations
- 1.6 Pin Descriptions
2. About Code Examples
3. AVR CPU Core
- 3.1 Introduction
- 3.2 Architectural Overview
- 3.3 ALU - Arithmetic Logic Unit
- 3.4 Status Register
- 3.5 General Purpose Register File
- 3.6 Stack Pointer
- 3.7 Instruction Execution Timing
- 3.8 Reset and Interrupt Handling
4. Memories
- 4.1 In-System Reprogrammable Flash Program Memory
- 4.2 SRAM Data Memory
- 4.3 EEPROM Data Memory
- 4.4 I/O Memory
- 4.5 External Memory Interface
- 4.6 General Purpose I/O Registers
5. System Clock
- 5.1 Clock Systems and their Distribution
- 5.2 Clock Sources
- 5.3 Default Clock Source
- 5.4 Crystal Oscillator
- 5.5 Low-frequency Crystal Oscillator
- 5.6 Calibrated Internal RC Oscillator
- 5.7 External Clock
- 5.8 Clock Output Buffer
- 5.9 Timer/Counter2 Oscillator
- 5.10 System Clock Prescaler
6. Power Management and Sleep Modes
- 6.1 Idle Mode
- 6.2 ADC Noise Reduction Mode
- 6.3 Power-down Mode
- 6.4 Power-save Mode
- 6.5 Standby Mode
- 6.6 Minimizing Power Consumption
7. System Control and Reset
- 7.1 Reset
- 7.2 Internal Voltage Reference
- 7.3 Watchdog Timer
- 7.4 Timed Sequences for Changing the Configuration of the Watchdog Timer
8. Interrupts
- 8.1 Interrupt Vectors in AT90CAN32/64/128
- 8.2 Moving Interrupts Between Application and Boot Space
9. I/O-Ports
- 9.1 Introduction
- 9.2 Ports as General Digital I/O
- 9.3 Alternate Port Functions
- 9.4 Register Description for I/O-Ports
10. External Interrupts
- 10.1 External Interrupt Register Description
11. Timer/Counter3/1/0 Prescalers
- 11.1 Overview
- 11.2 Timer/Counter0/1/3 Prescalers Register Description
12. 8-bit Timer/Counter0 with PWM
- 12.1 Features
- 12.2 Overview
- 12.3 Timer/Counter Clock Sources
- 12.4 Counter Unit
- 12.5 Output Compare Unit
- 12.6 Compare Match Output Unit
- 12.7 Modes of Operation
- 12.8 Timer/Counter Timing Diagrams
- 12.9 8-bit Timer/Counter Register Description
13. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- 13.1 Features
- 13.2 Overview
- 13.3 Accessing 16-bit Registers
- 13.4 Timer/Counter Clock Sources
- 13.5 Counter Unit
- 13.6 Input Capture Unit
- 13.7 Output Compare Units
- 13.8 Compare Match Output Unit
- 13.9 Modes of Operation
- 13.10 Timer/Counter Timing Diagrams
- 13.11 16-bit Timer/Counter Register Description
14. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 14.1 Features
- 14.2 Overview
- 14.3 Timer/Counter Clock Sources
- 14.4 Counter Unit
- 14.5 Output Compare Unit
- 14.6 Compare Match Output Unit
- 14.7 Modes of Operation
- 14.8 Timer/Counter Timing Diagrams
- 14.9 8-bit Timer/Counter Register Description
- 14.10 Asynchronous operation of the Timer/Counter2
- 14.11 Timer/Counter2 Prescaler
15. Output Compare Modulator - OCM
- 15.1 Overview
- 15.2 Description
16. Serial Peripheral Interface - SPI
- 16.1 Features
- 16.2 SS Pin Functionality
- 16.3 Data Modes
17. USART (USART0 and USART1)
- 17.1 Features
- 17.2 Overview
- 17.3 Dual USART
- 17.4 Clock Generation
- 17.5 Serial Frame
- 17.6 USART Initialization
- 17.7 Data Transmission - USART Transmitter
- 17.8 Data Reception - USART Receiver
- 17.9 Asynchronous Data Reception
- 17.10 Multi-processor Communication Mode
- 17.11 USART Register Description
- 17.12 Examples of Baud Rate Setting
18. Two-wire Serial Interface
- 18.1 Features
- 18.2 Two-wire Serial Interface Bus Definition
- 18.3 Data Transfer and Frame Format
- 18.4 Multi-master Bus Systems, Arbitration and Synchronization
- 18.5 Overview of the TWI Module
- 18.6 TWI Register Description
- 18.7 Using the TWI
- 18.8 Transmission Modes
- 18.9 Multi-master Systems and Arbitration
19. Controller Area Network - CAN
- 19.1 Features
- 19.2 CAN Protocol
- 19.3 CAN Controller
- 19.4 CAN Channel
- 19.5 Message Objects
- 19.6 CAN Timer
- 19.7 Error Management
- 19.8 Interrupts
- 19.9 CAN Register Description
- 19.10 General CAN Registers
- 19.11 MOb Registers
- 19.12 Examples of CAN Baud Rate Setting
20. Analog Comparator
- 20.1 Overview
- 20.2 Analog Comparator Register Description
- 20.3 Analog Comparator Multiplexed Input
21. Analog to Digital Converter - ADC
- 21.1 Features
- 21.2 Operation
- 21.3 Starting a Conversion
- 21.4 Prescaling and Conversion Timing
- 21.5 Changing Channel or Reference Selection
- 21.6 ADC Noise Canceler
- 21.7 ADC Conversion Result
- 21.8 ADC Register Description
22. JTAG Interface and On-chip Debug System
- 22.1 Features
- 22.2 Overview
- 22.3 Test Access Port - TAP
- 22.4 TAP Controller
- 22.5 Using the Boundary-scan Chain
- 22.6 Using the On-chip Debug System
- 22.7 On-chip Debug Specific JTAG Instructions
- 22.8 On-chip Debug Related Register in I/O Memory
- 22.9 Using the JTAG Programming Capabilities
- 22.10 Bibliography
23. Boundary-scan IEEE 1149.1 (JTAG)
- 23.1 Features
- 23.2 System Overview
- 23.3 Data Registers
- 23.4 Boundary-scan Specific JTAG Instructions
- 23.5 Boundary-scan Related Register in I/O Memory
- 23.6 Boundary-scan Chain
- 23.7 AT90CAN32/64/128 Boundary-scan Order
- 23.8 Boundary-scan Description Language Files
24. Boot Loader Support - Read-While-Write Self-Programming
- 24.1 Features
- 24.2 Application and Boot Loader Flash Sections
- 24.3 Read-While-Write and No Read-While-Write Flash Sections
- 24.4 Boot Loader Lock Bits
- 24.5 Entering the Boot Loader Program
- 24.6 Addressing the Flash During Self-Programming
- 24.7 Self-Programming the Flash
25. Memory Programming
- 25.1 Program and Data Memory Lock Bits
- 25.2 Fuse Bits
- 25.3 Signature Bytes
- 25.4 Calibration Byte
- 25.5 Parallel Programming Overview
- 25.6 Parallel Programming
- 25.7 SPI Serial Programming Overview
- 25.8 SPI Serial Programming
- 25.9 JTAG Programming Overview
26. Electrical Characteristics (1)
- 26.1 Absolute Maximum Ratings*
- 26.2 DC Characteristics
- 26.3 External Clock Drive Characteristics
- 26.4 Maximum Speed vs. VCC
- 26.5 Two-wire Serial Interface Characteristics
- 26.6 SPI Timing Characteristics
- 26.7 CAN Physical Layer Characteristics
- 26.8 ADC Characteristics
- 26.9 External Data Memory Characteristics
- 26.10 Parallel Programming Characteristics
27. Decoupling Capacitors
28. AT90CAN32/64/128 Typical Characteristics
- 28.1 Active Supply Current
- 28.2 Idle Supply Current
- 28.3 Power-down Supply Current
- 28.4 Power-save Supply Current
- 28.5 Standby Supply Current
- 28.6 Pin Pull-up
- 28.7 Pin Driver Strength
- 28.8 Pin Thresholds and Hysteresis
- 28.9 BOD Thresholds and Analog Comparator Offset
- 28.10 Internal Oscillator Speed
- 28.11 Current Consumption of Peripheral Units
- 28.12 Current Consumption in Reset and Reset Pulse Width
29. Register Summary
30. Instruction Set Summary
31. Ordering Information
32. Packaging Information
- 32.1 TQFP64
- 32.2 QFN64
33. Errata
- 33.1 Errata Summary
- 33.2 Errata Description
34. Datasheet Revision History for AT90CAN32/64/128
- 34.1 Changes from 7679G - 03/08 to 7679H - 08/08
- 34.2 Changes from 7679F - 11/07 to 7679G - 03/08
- 34.3 Changes from 7679E - 07/07 to 7679F - 11/07
- 34.4 Changes from 7679D - 02/07 to 7679E - 07/07
- 34.5 Changes from 7679C - 01/07 to 7679D - 02/07
- 34.6 Changes from 7679B - 11/06 to 7679C - 01/07
- 34.7 Changes from 7679A - 10/06 to 7679B - 11/06
- 34.8 Document Creation

342

7679H–CAN–08/08

AT90CAN32/64/128

25.6 Parallel Programming

25.6.1 Enter Programming Mode

The following algorithm puts the device in parallel programming mode:

1. Apply power between V

and GND.

2. Set RESET

to “0” and toggle XTAL1 at least six times.

3. Set the Prog_enable pins listed in Table 25-8 on page 340 to “0000” and wait at least

100 ns.

4. Apply 11.5 - 12.5V to RESET

. Any activity on Prog_enable pins within 100 ns after

+12V has been applied to RESET

, will cause the device to fail entering programming

mode.

5. Wait at least 50 µs before sending a new command.

25.6.2 Considerations for Efficient Programming

The loaded command and address are retained in the device during programming. For efficient

programming, the following should be considered.

• The command needs only be loaded once when writing or reading multiple memory

locations.

• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the

EESAVE Fuse is programmed) and Flash after a Chip Erase.

• Address high byte needs only be loaded before programming or reading a new 256 word

window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes

reading.

25.6.3 Chip Erase

The Chip Erase will erase the Flash and EEPROM

(1)

memories plus Lock bits. The Lock bits are

not reset until the program memory has been completely erased. The Fuse bits are not

changed. A Chip Erase must be performed before the Flash and/or EEPROM are

reprogrammed.

Load Command “Chip Erase”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR

a negative pulse. This starts the Chip Erase. RDY/BSY goes low.

6. Wait until RDY/BSY

goes high before loading a new command.

Note: 1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.

25.6.4 Programming the Flash

The Flash is organized in pages, see Table 25-11 on page 341. When programming the Flash,

the program data is latched into a page buffer. This allows one page of program data to be pro-

grammed simultaneously. The following procedure describes how to program the entire Flash

memory:

A: Load Command “Write Flash”