Datasheet

314
7679H–CAN–08/08
AT90CAN32/64/128
The recommended values from Table 23-7 are used unless other values are given in the algo-
rithm in Table 23-8. Only the DAC and port pin values of the Scan Chain are shown. The column
“Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register
with the succeeding columns. The verification should be done on the data scanned out when
scanning in the data on the same row in the table.
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t
hold,max
23.7 AT90CAN32/64/128 Boundary-scan Order
Table 23-9 shows the Scan order between TDI and TDO when the Boundary-scan chain is
selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The
scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in
the opposite bit order of the other ports. Exceptions from the rules are the Scan chains for the
analog circuits, which constitute the most significant bits of the scan chain regardless of which
physical pin they are connected to. In Figure 23-3, PXn. Data corresponds to FF0, PXn. Control
Table 23-8. Algorithm for Using the ADC
Step Actions ADCEN DAC MUXEN HOLD PRECH
PA3.
Data
PA3.
Control
PA3.
Pullup_
Enable
1
SAMPLE_
PRELOAD
1 0x200 0x08 1 1 0 0 0
2 EXTEST
1 0x200 0x08 0 1 0 0 0
3
1 0x200 0x08 1 1 0 0 0
4
1 0x123 0x08 1 1 0 0 0
5
1 0x123 0x08 1 0 0 0 0
6
Verify the
COMP bit
scanned out
to be 0
1 0x200 0x08 1 1 0 0 0
7
1 0x200 0x08 0 1 0 0 0
8
1 0x200 0x08 1 1 0 0 0
9
1 0x143 0x08 1 1 0 0 0
10
1 0x143 0x08 1 0 0 0 0
11
Verify the
COMP bit
scanned out
to be 1
1 0x200 0x08 1 1 0 0 0