Datasheet

303
7679H–CAN–08/08
AT90CAN32/64/128
23.4.1 EXTEST (0x0)
Mandatory JTAG instruction for selecting the Boundary-scan Chain as data register for testing
circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output
Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip
connections, the interface between the analog and the digital logic is in the scan chain. The con-
tents of the latched outputs of the Boundary-scan chain is driven out as soon as the JTAG IR-
Register is loaded with the EXTEST instruction.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Internal Scan Chain is shifted by the TCK input.
• Update-DR: Data from the scan chain is applied to output pins.
23.4.2 IDCODE (0x1)
Optional JTAG instruction selecting the 32 bit ID-Register as data register. The ID-Register con-
sists of a version number, a device number and the manufacturer code chosen by JEDEC. This
is the default instruction after power-up.
The active states are:
• Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain.
• Shift-DR: The IDCODE scan chain is shifted by the TCK input.
23.4.3 SAMPLE_PRELOAD (0x2)
Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the
input/output pins without affecting the system operation. However, the output latches are not
connected to the pins. The Boundary-scan Chain is selected as data register.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
• Update-DR: Data from the Boundary-scan chain is applied to the output latches. However,
the output latches are not connected to the pins.
23.4.4 AVR_RESET (0xC)
The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or
releasing the JTAG reset source. The TAP controller is not reset by this instruction. The one bit
Reset Register is selected as data register.
Note that the reset will be active as long as there is a logic “one” in the Reset Chain.
The output from this chain is not latched.
The active states are:
• Shift-DR: The Reset Register is shifted by the TCK input.
23.4.5 BYPASS (0xF)
Mandatory JTAG instruction selecting the Bypass Register for data register.
The active states are:
• Capture-DR: Loads a logic “0” into the Bypass Register.