Datasheet

141
7679H–CAN–08/08
AT90CAN32/64/128
13.11.9 Output Compare Register A – OCR1AH and OCR1AL
13.11.10 Output Compare Register B – OCR1BH and OCR1BL
13.11.11 Output Compare Register C – OCR1CH and OCR1CL
13.11.12 Output Compare Register A – OCR3AH and OCR3AL
13.11.13 Output Compare Register B – OCR3BH and OCR3BL
13.11.14 Output Compare Register C – OCR3CH and OCR3CL
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-
bit registers. See “Accessing 16-bit Registers” on page 116.
Bit 76543210
OCR1A[15:8] OCR1AH
OCR1A[7:0] OCR1AL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
OCR1B[15:8] OCR1BH
OCR1B[7:0] OCR1BL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
OCR1C[15:8] OCR1CH
OCR1C[7:0] OCR1CL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
OCR3A[15:8] OCR3AH
OCR3A[7:0] OCR3AL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
OCR3B[15:8] OCR3BH
OCR3B[7:0] OCR3BL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
OCR3C[15:8] OCR3CH
OCR3C[7:0] OCR3CL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000