Datasheet

36
3286P–MICRO–3/10
AT89S8253
18. Power-down Mode
In the power-down mode, the oscillator is stopped and the instruction that invokes power-down
is the last instruction executed. The on-chip RAM and Special Function Registers retain their
values until the power-down mode is terminated. Exit from power-down can be initiated either by
a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not
change the on-chip RAM. The reset should not be activated before V
CC
is restored to its normal
operating level and must be held active long enough to allow the oscillator to restart and
stabilize.
To exit power-down via an interrupt, external interrupt pin P3.2 or P3.3 must be kept low for at
least the specified required crystal oscillator start up time. Afterwards, the interrupt service rou-
tine starts at the rising edge of the external interrupt pin if the SFR bit AUXR.1 is set. If AUXR.1
is reset (cleared), execution starts after a self-timed interval of 2 ms (nominal) from the falling
edge of the external interrupt pin. The user should not attempt to enter (or re-enter) the power-
down mode for a minimum of 4 µs until after one of the following conditions has occurred: Start
of code execution (after any type of reset), or Exit from power-down mode.
19. Program Memory Lock Bits
The AT89S8253 has three lock bits that can be left unprogrammed (U) or can be programmed
(P) to obtain the additional features listed in Table 19-1. When lock bit 1 is programmed, the
logic level at the EA
pin is sampled and latched during reset. If the device is powered up without
a reset, the latch initializes to a random value and holds that value until reset is activated. The
latched value of EA
must agree with the current logic level at that pin in order for the device to
function properly. Once programmed, the lock bits can only be unprogrammed with the Chip
Erase operation in either the parallel or serial modes.
Note: 1. U = Unprogrammed; P = Programmed
Table 17-1. Status of External Pins During Idle and Power-down Modes
Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power-down Internal 0 0 Data Data Data Data
Power-down External 0 0 Float Data Data Data
Table 19-1. Lock Bit Protection Modes
(1)
Program Lock Bits
Protection TypeLB1 LB2 LB3
1 U U U No internal memory lock feature.
2PUU
MOVC instructions executed from external program memory are
disabled from fetching code bytes from internal memory. EA
is sampled
and latched on reset and further programming of the Flash memory
(parallel or serial mode) is disabled.
3 P P U Same as Mode 2, but parallel or serial verify are also disabled.
4 P P P Same as Mode 3, but external execution is also disabled.