Datasheet

28
3286P–MICRO–3/10
AT89S8253
Figure 14-4. SPI Master Timing (CPHA = 0)
Table 14-5. SPI Slave Characteristics
Symbol Parameter Min Max Units
t
CLCL
Oscillator Period 41.6 ns
t
SCK
Serial Clock Cycle Time 4t
CLCL
ns
t
SHSL
Clock High Time 1.5 t
CLCL
- 25 ns
t
SLSH
Clock Low Time 1.5 t
CLCL
- 25 ns
t
SR
Rise Time 25 ns
t
SF
Fall Time 25 ns
t
SIS
Serial Input Setup Time 10 ns
t
SIH
Serial Input Hold Time 10 ns
t
SOH
Serial Output Hold Time 10 ns
t
SOV
Serial Output Valid Time 35 ns
t
SOE
Output Enable Time 10 ns
t
SOX
Output Disable Time 25 ns
t
SSE
Slave Enable Lead Time 4 t
CLCL
+50 ns
t
SSD
Slave Disable Lag Time 0 ns
SS
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MISO
MOSI
t
SR
t
SCK
t
SLSH
t
SLSH
t
SHSL
t
SHSL
t
SOH
t
SF
t
SIS
t
SIH
t
SOV