Datasheet

27
3286P–MICRO–3/10
AT89S8253
Figure 14-3. SPI Shift Register Diagram
The CPHA (C
lock PHAse), CPOL (Clock POLarity), and SPR (Serial Peripheral clock Rate =
baud rate) bits in SPCR control the shape and rate of SCK. The two SPR bits provide four possi-
ble clock rates when the SPI is in master mode. In slave mode, the SPI will operate at the rate of
the incoming SCK as long as it does not exceed the maximum bit rate. There are also four pos-
sible combinations of SCK phase and polarity with respect to the serial data. CPHA and CPOL
determine which format is used for transmission. The SPI data transfer formats are shown in
Figure 14-4 and Figure 14-5. To prevent glitches on SCK from disrupting the interface, CPHA,
CPOL, and SPR should be set up before the interface is enabled, and the master device should
be enabled before the slave device(s).
Table 14-4. SPI Master Characteristics
Symbol Parameter Min Max Units
t
CLCL
Oscillator Period 41.6 ns
t
SCK
Serial Clock Cycle Time 4t
CLCL
ns
t
SHSL
Clock High Time t
SCK
/2 - 25 ns
t
SLSH
Clock Low Time t
SCK
/2 - 25 ns
t
SR
Rise Time 25 ns
t
SF
Fall Time 25 ns
t
SIS
Serial Input Setup Time 10 ns
t
SIH
Serial Input Hold Time 10 ns
t
SOH
Serial Output Hold Time 10 ns
t
SOV
Serial Output Valid Time 35 ns
2:1
MUX
2:1
MUX
Serial Master Serial Slave
LATCH
DQ
CLK
LATCH
DQ
CLK
LATCH
DQ
CLK
LATCH
DQ
CLK
Parallel Slave
(Read Buffer)
Parallel Master
(Write Buffer)
Serial Out
Receive
Byte
Serial In
Transmit
Byte
8 8
8
8
7
8