Datasheet

3286P–MICRO–3/10

AT89S8253

Table 14-2. SPSR – SPI Status Register

SPSR Address = AAH Reset Value = 000X XX00B

Not Bit Addressable

SPIF WCOL LDEN – – – DISSO ENH

Bit76543210

Symbol Function

SPIF

SPI interrupt flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if SPIE = 1 and ES

= 1. The SPIF bit is cleared by reading the SPI status register followed by reading/writing the SPI data register.

WCOL

When ENH = 0: Write collision flag. The WCOL bit is set if the SPI data register is written during a data transfer. During

data transfer, the result of reading the SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and

the SPIF bit) are cleared by reading the SPI status register followed by reading/writing the SPI data register.

When ENH = 1: WCOL works in Enhanced mode as Tx Buffer Full. Writing during WCOL = 1 in enhanced mode will

overwrite the waiting data already present in the Tx Buffer. In this mode, WCOL is no longer reset by the SPIF reset but

is reset when the write buffer has been unloaded into the serial shift register.

LDEN

Load enable for the Tx buffer in enhanced SPI mode.

When ENH is set, it is safe to load the Tx Buffer while LDEN = 1 and WCOL = 0. LDEN is high during bits 0 - 3 and is low

during bits 4 - 7 of the SPI serial byte transmission time frame.

DISSO

Disable slave output bit.

When set, this bit causes the MISO pin to be tri-stated so more than one slave device can share the same interface with

a single master. Normally, the first byte in a transmission could be the slave address and only the selected slave should

clear its DISSO bit.

ENH

Enhanced SPI mode select bit. When ENH = 0, SPI is in normal mode, i.e. without write double buffering.

When ENH = 1, SPI is in enhanced mode with write double buffering. The Tx buffer shares the same address with the

SPDR register.

Table 14-3. SPDR – SPI Data Register

SPDR Address = 86H

Reset Value = 00H (after cold reset)

unchanged (after warm reset)

Not Bit Addressable

SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0

Bit76543210