Datasheet

12
3286P–MICRO–3/10
AT89S8253
8. Programmable Watchdog Timer
The programmable Watchdog Timer (WDT) counts instruction cycles. The prescaler bits, PS0,
PS1 and PS2 in SFR WDTCON are used to set the period of the Watchdog Timer from 16K to
2048K instruction cycles. The available timer periods are shown in Table 8-1.
The WDT time-out
period is dependent upon the external clock frequency.
The WDT is disabled by Power-on Reset and during Power-down mode. When WDT times out
without being serviced or disabled, an internal RST pulse is generated to reset the CPU. See
Table 8-1 for the WDT period selections.
Table 8-1. Watchdog Timer Time-out Period Selection
WDT Prescaler Bits
Period (Nominal for
F
CLK
= 12 MHz)PS2 PS1 PS0
0 0 0 16 ms
0 0 1 32 ms
0 1 0 64 ms
011 128 ms
100 256 ms
101 512 ms
1 1 0 1024 ms
1 1 1 2048 ms