Datasheet

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3286P–MICRO–3/10
AT89S8253
7. Power-On Reset
A Power-On Reset (POR) is generated by an on-chip detection circuit. The detection level is
nominally 1.4V. The POR is activated whenever V
CC
is below the detection level. The POR cir-
cuit can be used to trigger the start-up reset or to detect a supply voltage failure in devices
without a brown-out detector. The POR circuit ensures that the device is reset from power-on.
When V
CC
reaches the Power-on Reset threshold voltage, the POR delay counter determines
how long the device is kept in POR after V
CC
rise, nominally 2 ms. The POR signal is activated
again, without any delay, when V
CC
falls below the POR threshold level. A Power-On Reset (i.e.
a cold reset) will set the POF flag in PCON.
Figure 7-1. Power-up and Brown-out Detection Sequence
7.1 Memory Brown-out Protection
The AT89S8253 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V
CC
level
during operation by comparing it to a fixed trigger level of nominally 2.2V (2.4V max). The pur-
pose of the BOD is to ensure that if V
CC
fails or dips, the Flash or EEPROM memories cannot be
erased/written at voltages too low for programming. At powerup the V
CC
level must pass the
BOD threshold before execution starts. When V
CC
decreases to a value below the trigger level,
the WRTINH
bit in EECON is activated and futher programming of the Flash/EEPROM is
restricted. When V
CC
increases above the trigger level, the BOD delay counter blocks program-
ming until after the timeout period has expired in approximately 2 ms. The BOD does not reset
the system as shown in Figure 7-1. To protect the system from errors induced by incorrect exe-
cution at lower voltages an external BOD circuit may be required.
POR
POR Level 1.4V
BOD Level 2.3V
Min V
CC
Level 2.7V
XTAL1
WRTINH
Internal
RESET
t
t
t
t
t
V
CC
t
POR
(2 ms)
t
POR
(2 ms)
2.4V
1.2V
0