Features • Compatible with MCS®51 Products • 12K Bytes of In-System Programmable (ISP) Flash Program Memory • • • • • • • • • • • • • • • • • • • • • • – SPI Serial Interface for Program Downloading – Endurance: 10,000 Write/Erase Cycles 2K Bytes EEPROM Data Memory – Endurance: 100,000 Write/Erase Cycles 64-byte User Signature Array 2.7V to 5.
The AT89S8253 provides the following standard features: 12K bytes of In-System Programmable Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector, four-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S8253 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.
AT89S8253 44J – 44-lead PLCC 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND NC (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4 (MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 6 5 4 3 2 1 44 43 42 41 40 P1.4 (SS) P1.3 P1.2 P1.1 (T2 EX) P1.
3.5 PWRGND Ground for the 42-PDIP which connects only the I/O Pad Drivers. PWRGND and GND are weakly connected through the common silicon substrate, but not through any metal links. The application board must connect both GND and PWRGND to the board ground. 3.6 Port 0 Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink six TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.
AT89S8253 3.9 Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source six TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the weak internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL,150 µA typical) because of the weak internal pull-ups. Port 3 receives some control signals for Flash programming and verification.
3.13 EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (V PP) during Flash programming when 12-volt programming is selected. 3.
AT89S8253 5. Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 5-1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will generally return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features.
5.1 Auxiliary Register Table 5-2. AUXR – Auxiliary Register AUXR Address = 8EH Reset Value = XXXX XXX0B Not Bit Addressable Bit – – – – – – Intel_Pwd_Exit DISALE 7 6 5 4 3 2 1 0 Symbol Function Intel_Pwd_Exit When set, this bit configures the interrupt driven exit from power-down to resume execution on the rising edge of the interrupt signal.
AT89S8253 5.5 Dual Data Pointer Registers To facilitate accessing both internal EEPROM and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H - 83H and DP1 at 84H - 85H. Bit DPS = 0 in SFR EECON selects DP0 and DPS = 1 selects DP1. The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register. 5.6 Power Off Flag The Power Off Flag (POF), located at bit_4 (PCON.4) in the PCON SFR.
In addition, during EEPROM programming, an attempted read from the EEPROM will fetch the byte being written with the MSB complemented. Once the write cycle is completed, true data are valid at all bit locations. 6.1 Memory Control Register The EECON register contains control bits for the 2K bytes of on-chip data EEPROM. It also contains the control bit for the dual data pointer. Table 6-1.
AT89S8253 7. Power-On Reset A Power-On Reset (POR) is generated by an on-chip detection circuit. The detection level is nominally 1.4V. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the start-up reset or to detect a supply voltage failure in devices without a brown-out detector. The POR circuit ensures that the device is reset from power-on.
8. Programmable Watchdog Timer The programmable Watchdog Timer (WDT) counts instruction cycles. The prescaler bits, PS0, PS1 and PS2 in SFR WDTCON are used to set the period of the Watchdog Timer from 16K to 2048K instruction cycles. The available timer periods are shown in Table 8-1. The WDT time-out period is dependent upon the external clock frequency. The WDT is disabled by Power-on Reset and during Power-down mode.
AT89S8253 8.1 Watchdog Control Register The WDTCON register contains control bits for the Watchdog Timer (shown in Table 8-2). Table 8-2. WDTCON – Watchdog Control Register WDTCON Address = A7H Reset Value = 0000 0000B Not Bit Addressable PS2 PS1 PS0 WDIDLE DISRTO HWDT WSWRST WDTEN 7 6 5 4 3 2 1 0 Bit Symbol Function PS2 PS1 PS0 Prescaler bits for the watchdog timer (WDT). When all three bits are cleared to 0, the watchdog timer has a nominal period of 16K machine cycles, (i.e.
9. Timer 0 and 1 Timer 0 and Timer 1 in the AT89S8253 operate the same way as Timer 0 and Timer 1 in the AT89S51 and AT89S52. For more detailed information on the Timer/Counter operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 10. Timer 2 Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (see Table 10-2 on page 15).
AT89S8253 Table 10-2. T2CON – Timer/Counter 2 Control Register T2CON Address = 0C8H Reset Value = 0000 0000B Bit Addressable Bit TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 7 6 5 4 3 2 1 0 Symbol Function TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1. EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
Figure 10-1. Timer 2 in Capture Mode ÷12 OSC C/T2 = 0 TH2 TL2 TF2 OVERFLOW CONTROL TR2 C/T2 = 1 CAPTURE T2 PIN RCAP2H RCAP2L TRANSITION DETECTOR TIMER 2 INTERRUPT T2EX PIN EXF2 CONTROL EXEN2 10.3 Auto-reload (Up or Down Counter) Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 10-3).
AT89S8253 value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt. Figure 10-2.
Figure 10-4. Timer 2 in Baud Rate Generator Mode TIMER 1 OVERFLOW ÷2 "0" "1" NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12 SMOD1 OSC ÷2 C/T2 = 0 "1" TH2 "0" TL2 RCLK CONTROL TR2 ÷16 Rx CLOCK C/T2 = 1 "1" "0" T2 PIN TCLK RCAP2H RCAP2L TRANSITION DETECTOR ÷ 16 T2EX PIN EXF2 Tx CLOCK TIMER 2 INTERRUPT CONTROL EXEN2 11. Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 10-2).
AT89S8253 Timer 2 as a baud rate generator is shown in Figure 10-4. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt.
13. UART The UART in the AT89S8253 operates the same way as the UART in the AT89S51 and AT89S52. For more detailed information on the UART operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 13.1 Enhanced UART In addition to all of its usual modes, the UART can perform framing error detection by looking for missing stop bits, and automatic address recognition.
AT89S8253 In the previous example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0.
Table 13-1. PCON – Power Control Register PCON Address = 87H Reset Value = 00xx 0000B Bit Addressable SMOD1 SMOD0 – POF GF1 GF0 PD IDL Bit 7 6 5 4 3 2 1 0 Symbol Function SMOD1 Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3. SMOD0 Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after a frame error regardless of the state of SMOD0. POF Power Off Flag. POF is set to “1” during power up (i.e.
AT89S8253 Notes: 1. SMOD0 is located at PCON.6. 2. fosc = oscillator frequency. 14. Serial Peripheral Interface The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the AT89S8253 and peripheral devices or between multiple AT89S8253 devices.
Figure 14-2. SPI Block Diagram S LSB S 8-BIT SHIFT REGISTER READ DATA BUFFER DIVIDER ÷4÷16÷64÷128 WRITE DATA BUFFER(1) CLOCK SPI CLOCK (MASTER) S CLOCK LOGIC MOSI P1.5 SCK 1.7 M SPR0 SELECT SPI STATUS REGISTER DORD SPR0 SPR1 CPHA CPOL MSTR SPE DORD 8 SPIE MSTR SPE WCOL SPI CONTROL SPE SS P1.4 MSTR SPR1 PIN CONTROL LOGIC MSB SPIF MISO P1.6 M M OSCILLATOR SPI CONTROL REGISTER 8 8 SPI INTERRUPT INTERNAL REQUEST DATA BUS Note: 1.
AT89S8253 Table 14-1. SPCR – SPI Control Register SPCR Address = D5H Reset Value = 0000 0100B Not Bit Addressable Bit SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 7 6 5 4 3 2 1 0 Symbol Function SPIE SPI interrupt enable. This bit, in conjunction with the ES bit in the IE register, enables SPI interrupts: SPIE = 1 and ES = 1 enable SPI interrupts. SPIE = 0 disables SPI interrupts. SPE SPI enable. SPI = 1 enables the SPI channel and connects SS, MOSI, MISO and SCK to pins P1.4, P1.5, P1.
Table 14-2. SPSR – SPI Status Register SPSR Address = AAH Reset Value = 000X XX00B Not Bit Addressable Bit SPIF WCOL LDEN – – – DISSO ENH 7 6 5 4 3 2 1 0 Symbol Function SPIF SPI interrupt flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if SPIE = 1 and ES = 1. The SPIF bit is cleared by reading the SPI status register followed by reading/writing the SPI data register. WCOL When ENH = 0: Write collision flag.
AT89S8253 Figure 14-3. SPI Shift Register Diagram 7 Serial In Serial Master 8 2:1 MUX D Serial Slave 2:1 MUX Q LATCH D Q Serial Out LATCH CLK CLK 8 Parallel Master Transmit Byte Parallel Slave (Write Buffer) 8 D (Read Buffer) 8 Q LATCH D Q 8 Receive Byte LATCH CLK CLK The CPHA (Clock PHAse), CPOL (Clock POLarity), and SPR (Serial Peripheral clock Rate = baud rate) bits in SPCR control the shape and rate of SCK.
Table 14-5. SPI Slave Characteristics Symbol Parameter Min Max Units tCLCL Oscillator Period 41.6 ns tSCK Serial Clock Cycle Time 4tCLCL ns tSHSL Clock High Time 1.5 tCLCL - 25 ns tSLSH Clock Low Time 1.
AT89S8253 Figure 14-5. SPI Slave Timing (CPHA = 0) SS tSR tSCK tSSE SCK (CPOL = 0) SCK (CPOL= 1) tSHSL tSLSH tSLSH tSHSL tSOV tSOE tSSD tSF tSOX tSOH MISO tSIS tSIH MOSI Figure 14-6. SPI Master Timing (CPHA = 1) SS tSCK SCK (CPOL = 0) SCK (CPOL = 1) tSF tSHSL tSLSH tSLSH tSHSL tSR tSIS tSIH MISO tSOV tSOH MOSI Figure 14-7.
Figure 14-8. SPI Transfer Format with CPHA = 0 Note: *Not defined but normally MSB of character just received Figure 14-9. SPI Transfer Format with CPHA = 1 SCK CYCLE # (FOR REFERENCE) 1 2 3 4 5 6 7 8 SCK (CPOL = 0) SCK (CPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) * MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB LSB SS (TO SLAVE) Note: *Not defined but normally LSB of previously transmitted character 15.
AT89S8253 Interrupt Source Vector Address System Reset RST or POR 0000H External Interrupt 0 IE0 0003H Timer 0 Overflow TF0 000BH External Interrupt 1 IE1 0013H Timer 1 Overflow TF1 001BH Serial Port RI or TI or SPIF 0023H Table 15-1. Interrupt Enable (IE) Register IE Address = A8H Reset Value = 0X00 0000B Bit Addressable EA – ET2 ES ET1 EX1 ET0 EX0 Enable Bit = 1 enables the interrupt, 0 disables the interrupt. Symbol Position Function EA IE.
. Table 15-3. IPH – Interrupt Priority High Register IPH = B7H Reset Value = XX00 0000B Not Bit Addressable Bit – – PT2H PSH PT1H PX1H PT0H PX0H 7 6 5 4 3 2 1 0 Symbol Function PT2H Timer 2 Interrupt Priority High PSH Serial Port Interrupt Priority High PT1H Timer 1 Interrupt Priority High PX1H External Interrupt 1 Priority High PT0H Timer 0 Interrupt Priority High PX0H External Interrupt 0 Priority High Figure 15-1.
AT89S8253 16. Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 16-1 (A) and (B). Either a quartz crystal or ceramic resonator may be used. For frequencies above 16MHz it is recommended that C1 be replaced with R1 for improved startup performance. Note that the internal structure of the devices adds about 10 pF of capacitance to both XTAL1 and XTAL2.
Figure 16-3. Quartz Crystal Clock Source (B) Quartz Crystal Clock Input XTAL1 Amplitude (V) 7 C2=0pF 6 C2=5pF 5 C2=10pF 4 R1=4MΩ 3 2 1 0 0 4 8 12 16 20 24 Frequency (MHz) Figure 16-4.
AT89S8253 Figure 16-5. Ceramic Resonator Clock Source (B) Ceramic Resonator Clock Input XTAL1 Amplitude (V) 7 C2=0pF 6 C2=5pF 5 C2=10pF 4 R1=4MΩ 3 2 1 0 0 4 8 12 16 20 24 Frequency (MHz) To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 16-6. Figure 16-6. External Clock Drive Configuration 17. Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active.
Table 17-1. Status of External Pins During Idle and Power-down Modes Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3 Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power-down Internal 0 0 Data Data Data Data Power-down External 0 0 Float Data Data Data 18. Power-down Mode In the power-down mode, the oscillator is stopped and the instruction that invokes power-down is the last instruction executed.
AT89S8253 20. Programming the Flash and EEPROM Atmel’s AT89S8253 Flash microcontroller offers 12K bytes of In-System reprogrammable Flash code memory and 2K bytes of EEPROM data memory. The AT89S8253 is normally shipped with the on-chip Flash code and EEPROM data memory arrays in the erased state (i.e. contents = FFH) and ready to be programmed. This device supports a parallel programming mode and a serial programming mode.
10. Repeat steps 4 through 7 changing the address and data for the entire array or until the end of the object file is reached. 11. Power-off sequence: a. Tri-state the address and data inputs. b. Disable the P3.0 pullup used for RDY/BUSY operation. c. Set XTAL1 to “L”. d. Set RST and EA pins to “L”. e. Turn VCC power off. Data Polling: The AT89S8253 features DATA Polling to indicate the end of any programming cycle.
AT89S8253 21. Programming Interface Every code byte in the Flash and EEPROM arrays can be written, and the entire array can be erased, by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. Most worldwide major programming vendors offer support for the Atmel AT89 microcontroller series. Please contact your local programming vendor for the appropriate software revision. 22.
24. Serial Programming Instruction The Instruction Set for Serial Programming follows a 4-byte protocol and is shown in Table 24-1. Table 24-1.
AT89S8253 25. Flash and EEPROM Parallel Programming Modes ALE Mode Serial Prog. Modes Chip Erase (1) (2) (3)(4)(5) Address P2.5:0, P1.7:0 EA P3.3 P3.4 P3.5 P3.6 P3.7 Data I/O P0.7:0 1.0 µs 12V H L H L L X X RST PSEN H h h H L Page Write 12K Code H L 1.0 µs 12V L H H H H DI ADDR Read 12K Code H L H 12V L L H H H DO ADDR Page Write 2K Data H L 1.
Fuse3 (User Row Access Fuse): This fuse enables/disables writing to the programmable user row. Fuse4 (Clock Selection Fuse): This fuse selects between an external clock source and a quartz crystal as the clock input. Programming the Flash/EEPROM Memory (Parallel Mode) VCC VCC AT89S8253 A0 - A7 ADDR. 0000H/37FFH AT89S8253 PGM DATA P0 P2.0 - P2.5 A8 - A13 P3.3 P3.6 P2.0 - P2.5 P3.3 P3.4 SEE FLASH PROGRAMMING MODES TABLE P3.5 VCC P1 PGM DATA P0 A8 - A13 PROG ALE P3.
AT89S8253 Figure 25-3. Flash/EEPROM Serial Downloading 2.7V to 5.5V 2.7V to 5.5V AT89S8253 AT89S8253 VCC VCC INSTRUCTION INPUT P1.5/MOSI INSTRUCTION INPUT P1.5/MOSI DATA OUTPUT P1.6/MISO DATA OUTPUT P1.6/MISO CLOCK IN P1.7/SCK CLOCK IN P1.
26. Flash Programming and Verification Characteristics – Parallel Mode TA = 20°C to 30°C, VCC = 4.0V to 5.5V Symbol Parameter Min Max Units VPP Programming Enable Voltage 11.5 12.5 V IPP Programming Enable Current 1.
3286P–MICRO–3/10 P3.0 (RDY/BSY) PORT 0 P1.0...P1.7 and P2.0...P2.5 P3.3...P3.7 ALE/PROG EA/VPP PSEN XTAL 1 RST VCC tPSTP tOSTL tRHX tPWRUP tHSTL tDSTP tASTP tPGW DATA0 ADDR0 tMSTP Running at 3 MHz DATA1 ADDR1 tDHLD tAHLD tBLT tPHBL tWC tMHLD tVFY DATA1 ADDR1 DATA0 ADDR0 tMSTP tPHLD tPLX tXRL tPWRDN AT89S8253 Figure 26-1.
27. Serial Downloading Waveforms (SPI Mode 1 −−> CPOL = 0, CPHA = 1) 7 6 4 5 3 2 1 0 SERIAL DATA INPUT MOSI/P1.5 MSB LSB MSB LSB SERIAL DATA OUTPUT MISO/P1.6 SCK/P1.7 28. Serial Programming Characteristics Figure 28-1. Serial Programming Timing Change Outputs Sample Inputs t SLSH t SHSL SCK t OVSL t SHOX MOSI MISO t SHIV Table 28-1. Serial Programming Characteristics, TA = -40° C to 85° C, VCC = 2.7V - 5.
AT89S8253 29. Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage ............................................ 6.6V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
31. AC Characteristics The values shown in this table are valid for TA = -40°C to 85°C and VCC = 2.7 to 5.5V, unless otherwise noted. Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. 31.
AT89S8253 32. External Program Memory Read Cycle 33.
34. External Data Memory Write Cycle 35. External Clock Drive Waveforms 36. External Clock Drive VCC = 2.7V to 5.5V Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Clock Period tCHCX Min Max Units 0 24 MHz 41.
AT89S8253 37. Serial Port Timing: Shift Register Mode Test Conditions Variable Oscillator Symbol Parameter Min Max Units 38. Shift Register Mode Timing Waveforms 39. AC Testing Input/Output Waveforms(1) Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0. 40.
41. ICC Test Condition, Active Mode, All Other Pins are Disconnected VCC ICC VCC RST VCC P0 EA XTAL2 (NC) CLOCK SIGNAL XTAL1 VSS 42. ICC Test Condition, Idle Mode, All Other Pins are Disconnected VCC ICC VCC RST VCC P0 EA XTAL2 (NC) CLOCK SIGNAL XTAL1 VSS 43. Clock Signal Waveform for ICC Tests in Active and Idle Modes, tCLCH = tCHCL = 5 ns VCC - 0.5V 0.45V 0.7 VCC tCHCX 0.2 VCC - 0.1V tCHCL tCLCH tCHCX tCLCL 44.
AT89S8253 45. ICC (Active Mode) Measurements o AT89S8253 ICC Active @ 25 C With Internal Clock Oscillator x1 Mode ICC Active (mA) 4.00 3.50 3.0V 3.00 4.0V 2.50 5.0V 2.00 1.50 1 2 3 4 5 6 7 8 9 10 11 12 Frequency (MHz) o AT89S8253 ICC Active @ 90 C With Internal Clock Oscillator x1 Mode ICC Active (mA) 4.00 3.50 3.0V 3.00 4.0V 2.50 5.0V 2.00 1.
46. ICC (Idle Mode) Measurements AT89S8253 ICC Idle vs. Frequency, T = 25°C With Internal Clock Oscillator x1 Mode 3 ICC (mA) 2.5 2 Vcc=3V Vcc=4V 1.5 Vcc=5V 1 0.5 0 0 5 10 15 20 25 Frequency (MHz) 47. ICC (Power Down Mode) Measurements AT89S8253 ICC in Power-down ICC Pwd (uA) 2.5 2 0 deg C 1.5 25 deg C 1 90 deg C 0.
AT89S8253 48. Ordering Information 48.1 Green Package (Pb/Halide-free) Speed (MHz) 24 Power Supply 2.7V to 5.5V Ordering Code Package AT89S8253-24AU AT89S8253-24JU AT89S8253-24PU AT89S8253-24PSU 44A 44J 40P6 42PS6 Operation Range Industrial (-40° C to 85° C) Package Type 44A 44-lead, Thin Plastic Gull Wing Quad Flat Package (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 42PS6 42-lead, 0.
49. Package Information 49.1 44A – TQFP PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.
AT89S8253 49.2 44J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
49.3 40P6 – PDIP D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF MIN NOM MAX A – – 4.826 A1 0.381 – – D 52.070 – 52.578 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.556 C 0.203 – 0.381 eB 15.494 – 17.526 SYMBOL eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion.
AT89S8253 49.4 42PS6 – PDIP D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = Inch) C eC eB Notes: 1. This package conforms to JEDEC reference MS-020, Variation AB. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). MIN NOM MAX A – – 0.200 A1 0.020 – – D 1.440 1.450 1.460 E 0.600 – 0.630 E1 0.500 0.540 0.570 B 0.015 0.018 0.022 B1 0.035 0.040 0.045 L 0.100 0.
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