Datasheet

ManualsBrandsMicrochip Manuals8051 MicrocontrollersLow Power, High Performance CMOS Microcontroller 8bit 20KB PDIP

Features

• Compatible with MCS

-51 Products

• 20K Bytes of Reprogrammable Flash Memory

• Endurance: 10,000 Write/Erase Cycles

• 4V to 5.5V Operating Range

• Fully Static Operation: 0 Hz to 33 MHz

• Three-level Program Memory Lock

• 256 x 8-bit Internal RAM

• 32 Programmable I/O Lines

• Three 16-bit Timer/Counters

• Eight Interrupt Sources

• Programmable Serial Channel

• Low-power Idle and Power-down Modes

• Interrupt Recovery from Power-down Mode

• Hardware Watchdog Timer

• Dual Data Pointer

• Power-off Flag

• Green (Pb/Halide-free) Packaging Option

1. Description

The AT89C55WD is a low-power, high-performance CMOS 8-bit microcontroller with

20K bytes of Flash programmable read only memory and 256 bytes of RAM. The

device is manufactured using Atmel’s high-density nonvolatile memory technology

and is compatible with the industry standard 80C51 and 80C52 instruction set and

pinout. The on-chip Flash allows the program memory to be user programmed by a

conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU

with Flash on a monolithic chip, the Atmel AT89C55WD is a powerful microcomputer

which provides a highly flexible and cost effective solution to many embedded control

applications.

The AT89C55WD provides the following standard features: 20K bytes of Flash, 256

bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector, two-level interrupt

architecture, a full-duplex serial port, on-chip oscillator, and clock circuitry. In addition,

the AT89C55WD is designed with static logic for operation down to zero frequency

and supports two software selectable power saving modes. The Idle Mode stops the

CPU while allowing the RAM, timer/counters, serial port, and interrupt system to con-

tinue functioning. The Power-down Mode saves the RAM contents but freezes the

oscillator, disabling all other chip functions until the next external interrupt or hardware

reset.

1921D–MICRO–6/08

8-bit

Microcontroller

with 20K Bytes

Flash

AT89C55WD

Summary of content (35 pages)

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Features • • • • • • • • • • • • • • • • • Compatible with MCS®-51 Products 20K Bytes of Reprogrammable Flash Memory Endurance: 10,000 Write/Erase Cycles 4V to 5.
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. Pin Configurations 44A – 44-lead TQFP 44 43 42 41 40 39 38 37 36 35 34 P1.4 P1.3 P1.2 P1.1 (T2 EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) 2.1 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND GND (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4 12 13 14 15 16 17 18 19 20 21 22 P1.5 P1.6 P1.7 RST (RXD) P3.0 NC (TXD) P3.
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AT89C55WD 3. Block Diagram P0.0 - P0.7 P2.0 - P2.7 PORT 0 DRIVERS PORT 2 DRIVERS VCC GND RAM ADDR. REGISTER B REGISTER PORT 0 LATCH RAM QUICK FLASH PORT 2 LATCH STACK POINTER ACC BUFFER TMP1 TMP2 PROGRAM ADDRESS REGISTER PC INCREMENTER ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PROGRAM COUNTER PSW PSEN ALE/PROG EA / VPP TIMING AND CONTROL DUAL DPTR INSTRUCTION REGISTER RST WATCH DOG PORT 1 LATCH PORT 3 LATCH PORT 1 DRIVERS PORT 3 DRIVERS OSC P1.0 - P1.7 P3.0 - P3.
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. Pin Description 4.1 VCC Supply voltage. 4.2 GND Ground. 4.3 Port 0 Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups.
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AT89C55WD 4.6 Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification.
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4.10 EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12V programming enable voltage (VPP) during Flash programming. 4.
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AT89C55WD Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.
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Table 5-3.
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AT89C55WD 6. Memory Organization The MCS-51 devices have a separate address space for Program and Data Memory. Up to 64 Kbytes each of external Program and Data Memory can be addressed. 6.1 Program Memory If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89C55WD, if EA is connected to VCC, program fetches to addresses 0000H through 4FFFH are directed to internal memory and fetches to addresses 5000H through FFFFH are to external memory. 6.
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8. Using the WDT To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 13-bit counter overflows when it reaches 8191 (1FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must re-initialize the WDT at least every 8191 machine cycles.
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AT89C55WD 12. Timer 2 Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 5-2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 5-2. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle.
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Figure 12-1. Timer in Capture Mode ÷12 OSC C/T2 = 0 TH2 TL2 OVERFLOW CONTROL C/T2 = 1 TF2 TR2 CAPTURE T2 PIN RCAP2H RCAP2L TRANSITION DETECTOR TIMER 2 INTERRUPT T2EX PIN EXF2 CONTROL EXEN2 Figure 12-2 shows Timer 2 automatically counting up when DCEN=0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow.
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AT89C55WD Table 12-2. T2MOD – Timer 2 Mode Control Register T2MOD Address = 0C9H Reset Value = XXXX XX00B Not Bit Addressable Bit – – – – – – T2OE DCEN 7 6 5 4 3 2 1 0 Symbol Function – Not implemented, reserved for future T2OE Timer 2 Output Enable bit DCEN When set, this bit allows Timer 2 to be configured as an up/down counter Figure 12-3.
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13. Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 5-2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 13-1.
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AT89C55WD Figure 13-1. Timer 2 in Baud Rate Generator Mode TIMER 1 OVERFLOW ÷2 "0" "1" NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12 SMOD1 OSC ÷2 C/T2 = 0 "1" TH2 "0" TL2 RCLK CONTROL TR2 ÷ 16 Rx CLOCK C/T2 = 1 "1" "0" T2 PIN TCLK RCAP2H RCAP2L TRANSITION DETECTOR ÷ 16 T2EX PIN EXF2 Tx CLOCK TIMER 2 INTERRUPT CONTROL EXEN2 14. Programmable Clock Out A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 14-1.
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Figure 14-1. Timer 2 in Clock-Out Mode TL2 (8-BITS) ÷2 OSC TH2 (8-BITS) TR2 RCAP2L RCAP2H C/T2 BIT P1.0 (T2) ÷2 T2OE (T2MOD.1) TRANSITION DETECTOR P1.1 (T2EX) EXF2 TIMER 2 INTERRUPT EXEN2 15. Interrupts The AT89C55WD has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 15-1.
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AT89C55WD The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows. Table 15-1. Interrupt Enable (IE) Register (MSB) EA (LSB) – ET2 ES ET1 EX1 ET0 EX0 Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt. Symbol Position Function EA IE.
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16. Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 18-1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 18-2.
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AT89C55WD Figure 18-1. Oscillator Connections C2 XTAL2 C1 XTAL1 GND Note: C1, C2 = 30 pF ± 10 pF for Crystals = 40 pF ± 10 pF for Ceramic Resonators Figure 18-2. External Clock Drive Configuration NC XTAL2 EXTERNAL OSCILLATOR SIGNAL XTAL1 GND Table 18-1.
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19. Program Memory Lock Bits The AT89C55WD has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the following table. Table 19-1. Lock Bit Protection Modes Program Lock Bits 1 LB1 LB2 LB3 Protection Type U U U No program lock features.
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AT89C55WD Chip Erase Sequence: Before the AT89C55WD can be reprogrammed, a Chip Erase operation needs to be performed. To erase the contents of the AT89C55WD, follow this sequence: 1. Raise VCC to 6.5V. 2. Pulse ALE/PROG once (duration of 200 - 500 ns). 3. Wait for 150 ms. 4. Power VCC down and up to 6.5V. 5. Pulse ALE/PROG once (duration of 200 - 500 ns). 6. Wait for 150 ms. 7. Power VCC down and up. Data Polling: The AT89C55WD features Data Polling to indicate the end of a write cycle.
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Table 21-1. Mode Flash Programming Modes VCC RST PSEN ALE/ PROG P3.4 P2.5-0 P1.7-0 EA/ VPP P2.6 P2.7 P3.3 P3.6 P3.7 P0.7-0 Data 12V L H H H H DIN A14 A13-8 A7-0 H/12V L L L H H DOUT A14 A13-8 A7-0 12V H H H H H X X X X 12V H H H L L X X X X 12V H L H H L X X X X H H H L H L P0.2, P0.3, P0.4 X X X 12V H L H L L X X X X Address (1) Write Code Data 5V H L Read Code Data 5V H L Write Lock Bit 1 6.
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AT89C55WD Figure 21-1. Programming the Flash Memory 4.5V to 5.5V AT89C55WD ADDR. 0000H/4FFFH A0 - A7 A8 - A13 A14* SEE FLASH PROGRAMMING MODES TABLE P1.0 - P1.7 VCC P2.0 - P2.5 P3.4 P2.6 P2.7 P3.3 P3.6 P0 PGM DATA ALE PROG EA VIH /VPP P3.7 XTAL2 3 - 33 MHz XTAL1 GND P3.0 RDY/ BSY RST VIH PSEN Figure 21-2. Verifying the Flash Memory 4.5V to 5.5V AT89C55WD A0 - A7 ADDR. 0000H/4FFFH P1.0 - P1.7 VCC P2.0 - P2.5 P3.4 P2.6 P2.7 P3.3 P3.6 P3.
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22. Flash Programming and Verification Characteristics TA = 20°C to 30°C, VCC = 4.5V to 5.5V Symbol Parameter Min Max Units VPP Programming Supply Voltage 11.5 12.5 V IPP Programming Supply Current 10 mA ICC VCC Supply Current 30 mA 1/tCLCL Oscillator Frequency 33 MHz tAVGL Address Setup to PROG Low 48tCLCL tGHAX Address Hold After PROG 48tCLCL tDVGL Data Setup to PROG Low 48tCLCL tGHDX Data Hold After PROG 48tCLCL tEHSH P2.
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AT89C55WD 23. Flash Programming and Verification Waveforms PROGRAMMING ADDRESS P1.0 - P1.7 P2.0 - P2.5 P3.4 VERIFICATION ADDRESS tAVQV PORT 0 DATA IN tAVGL tDVGL tGHDX DATA OUT tGHAX ALE/PROG tSHGL tGHSL tGLGH VPP LOGIC 1 LOGIC 0 EA/VPP tEHSH tEHQZ tELQV P2.7 (ENABLE) tGHBL P3.0 (RDY/BSY) BUSY READY tWC 24. Lock Bit Programming Test Conditions Setup Lockbit_1, 2 or 3 Data Setup 100 µs ALE/PROG VCC = 4.5V to 5.5V VCC = 6.5V Wait 10 ms to reload new lock bit status 25.
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. Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage ............................................ 6.6V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
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AT89C55WD 28. AC Characteristics Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. 28.
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29. External Program Memory Read Cycle tLHLL ALE tAVLL tLLIV tLLPL tPLIV PSEN tPXAV tPLAZ tPXIZ tLLAX tPXIX A0 - A7 PORT 0 tPLPH INSTR IN A0 - A7 tAVIV A8 - A15 PORT 2 A8 - A15 30. External Data Memory Read Cycle tLHLL ALE tWHLH PSEN tLLDV tRLRH tLLWL RD tLLAX tAVLL PORT 0 tRLDV tRLAZ A0 - A7 FROM RI OR DPL tRHDZ tRHDX DATA IN A0 - A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 28 P2.0 - P2.
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AT89C55WD 31. External Data Memory Write Cycle tLHLL ALE tWHLH PSEN tLLWL WR tAVLL tLLAX tQVWX A0 - A7 FROM RI OR DPL PORT 0 tWLWH tQVWH DATA OUT tWHQX A0 - A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH 32. External Clock Drive Waveforms tCHCX VCC - 0.5V tCHCX tCLCH tCHCL 0.7 VCC 0.2 VCC - 0.1V 0.45V tCLCX tCLCL 33.
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34. Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for VCC = 4.0V to 5.5V and Load Capacitance = 80 pF. 12 MHz Osc Variable Oscillator Symbol Parameter Min Max Min Max tXLXL Serial Port Clock Cycle Time 1.
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AT89C55WD 38. Ordering Information 38.1 Green Package Option (Pb/Halide-free) Speed (MHz) Power Supply 24 33 Ordering Code Package Operation Range 4.0V to 5.5V AT89C55WD-24AU AT89C55WD-24JU AT89C55WD-24PU 44A 44J 40P6 Industrial (-40° C to 85° C) 4.5V to 5.5V AT89C55WD-33AU AT89C55WD-33JU AT89C55WD-33PU 44A 44J 40P6 Industrial (-40° C to 85° C) Package Type 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-pin, 0.
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39. Package Information 39.1 44A – TQFP PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.
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AT89C55WD 39.2 44J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
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39.3 40P6 – PDIP D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF MIN NOM MAX A – – 4.826 A1 0.381 – – D 52.070 – 52.578 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.556 C 0.203 – 0.381 eB 15.494 – 17.526 SYMBOL eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion.
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