Datasheet

998
32117D–AVR-01/12
AT32UC3C
• PREA, PREB: CLKA, CLKB Source Clock Selection
• DIVA, DIVB: CLKA, CLKB Divide Factor
Table 33-4. Source Clock Selection
PREA, PREB Divider Input Clock
0 CCK
1 CCK/2
2 CCK/4
3 CCK/8
4 CCK/16
5 CCK/32
6 CCK/64
7 CCK/128
8 CCK/256
9 CCK/512
10 CCK/1024
Other Reserved
Table 33-5. Divide Factor
DIVA/DIVB CLKA/CLKB
0 CLKA/CLKB clock is turned off
1 CLKA/CLKB clock is selected by PREA/PREB
2 - 255 CLKA/CLKB clock is selected by PREA/PREB divided by DIVA/DIVB factor