Datasheet

997
32117D–AVR-01/12
AT32UC3C
33.7.1 Clock Register
Name:
CLK
Access Type: Read/Write
Offset: 0x000
Reset Value: 0x00000000
This register can only be written if the WPSWS0 and WPHWS0 bits are cleared in ”Write Protect Status Register” on page
1030.
• CLKSEL: CCK Source Clock Selection
0: The PWM internal clock CCK is driven by the master clock CLK_PWM.
1: The PWM internal clock CCK is driven by the generic clock GCLK.
CAUTION: After writing CLKSEL to a new value, no write to any PWM registers must be attempted before a delay of 2
master clock periods (CLK_PWM). This is the time needed by the PWM to switch the internal clock CCK.
31 30 29 28 27 26 25 24
CLKSEL --- PREB
23 22 21 20 19 18 17 16
DIVB
15 14 13 12 11 10 9 8
---- PREA
76543210
DIVA