Datasheet

996

32117D–AVR-01/12

AT32UC3C

Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the

end of this chapter.

2. Some registers are indexed with “ch_num” index ranging from 0 to 3.

0x1A8 Comparison 7 Mode Register CMP7M Read/Write 0x000000000

0x1AC Comparison 7 Mode Update Register CMP7MUPD Write-only –

0x1B0 - 0x1FC Reserved – – –

0x200 + ch_num *

0x20 + 0x00

Channel Mode Register CMR Read/Write 0x000000000

0x200 + ch_num *

0x20 + 0x04

Channel Duty Cycle Register CDTY Read/Write 0x000000000

0x200 + ch_num *

0x20 + 0x08

Channel Duty Cycle Update Register CDTYUPD Write-only –

0x200 + ch_num *

0x20 + 0x0C

Channel Period Register CPRD Read/Write 0x000000000

0x200 + ch_num *

0x20 + 0x10

Channel Period Update Register CPRDUPD Write-only –

0x200 + ch_num *

0x20 + 0x14

Channel Counter Register CCNT Read-only 0x000000000

0x200 + ch_num *

0x20 + 0x18

Channel Dead Time Register DT Read/Write 0x000000000

0x200 + ch_num *

0x20 + 0x1C

Channel Dead Time Update Register DTUPD Write-only –

Table 33-3. PWM Register Memory Map

(2)

Offset Register

Name Access Reset