Datasheet

993
32117D–AVR-01/12
AT32UC3C
33.6.5.7 Write Protect Registers
To prevent any single software error that may corrupt PWM behavior, the registers listed below
can be write-protected by writing the WPCMD field in the ”Write Protect Control Register” on
page 1028 (WPCR). They are divided into 6 groups:
• Register group 0:
– ”Clock Register” on page 997
• Register group 1:
– ”Disable Register” on page 1000
• Register group 2:
– ”Sync Channels Mode Register” on page 1006
– ”Channel Mode Register” on page 1036
– ”Stepper Motor Mode Register” on page 1027
• Register group 3:
– ”Channel Period Register” on page 1040
– ”Channel Period Update Register” on page 1042
• Register group 4:
– ”Channel Dead Time Register” on page 1045
– ”Channel Dead Time Update Register” on page 1046
• Register group 5:
– ”Fault Mode Register” on page 1021
– ”Fault Protection Value Register” on page 1024
There are two types of Write Protect:
• the Write Protect SW, which can be enabled or disabled.
• the Write Protect HW, which can just be enabled, only a hardware reset of the PWM
controller can disable it.
Both Write Protect can be applied independently to a particular register group thanks to the
WPCMD and WPRG fields in WPCR register. If at least one of the Write Protect is active, the
register group is write-protected. The WPCMD field allows to perform the following actions
depending on its value:
• 0: Disabling the Write Protect SW of the register groups of which the WPRG bit is at 1.
• 1: Enabling the Write Protect SW of the register groups of which the WPRG bit is at 1.
• 2: Enabling the Write Protect HW of the register groups of which the WPRG bit is at 1.
At any time, the user can know which Write Protect is active in which register group by the
WPSWS and WPHWS fields in the ”Write Protect Status Register” on page 1030 (WPSR).
If a write access in a write-protected register is detected, then the WPVS bit in the WPSR regis-
ter is set and the WPVSRC field indicates in which register the write access has been attempted,
through its address offset without the two LSBs.
The WPVS and WPSR fields are automatically reset after reading the WPSR register.