Datasheet

992
32117D–AVR-01/12
AT32UC3C
UPR in ”Sync Channels Update Period Register” on page 1009 (SCUP)) and the end of the cur-
rent PWM period, then updates the value for the next period.
Note: If the SCUPUPD update register is written several times between two updates, only the last writ-
ten value is taken into account.
Note: Changing the update period does make sense only if there is one or more synchronous channels
and if the update method 1 or 2 is selected (UPDM=1 or 2 in ”Sync Channels Mode Register” on
page 1006).
33.6.5.5 Changing the Comparison Value and the Comparison Configuration
It is possible to change the comparison values and the comparison configurations while the
channel 0 is enabled (see Section 33.6.3 on page 987).
To prevent unexpected comparison match, the user must use the ”Comparison x Value Update
Register” on page 1033 and the ”PWM Comparison x Mode Update Register” on page 1035
(CMPxVUPD and CMPxMUPD) to change respectively the comparison values and the compari-
son configurations while the channel 0 is still enabled. These registers hold the new values until
the end of the comparison update period (when CUPRCNT is equal to CUPR in ”Comparison x
Mode Register” on page 1034 (CMPxM)) and the end of the current PWM period, then update
the values for the next period.
CAUTION: to be taken into account, the write of the CMPxVUPD register must be followed by a
write of the CMPxMUPD register.
Note: If the update registers CMPxVUPD and CMPxMUPD are written several times between two
updates, only the last written value are taken into account.
33.6.5.6 Interrupts
Depending on the interrupt mask in the IMR1 and IMR2 registers, an interrupt can be generated
at the end of the corresponding channel period (CHIDx in the ISR1 register), after a fault event
(FCHIDx in the ISR1 register), after a comparison match (CMPMx in the ISR2 register), after a
comparison update (CMPUx in the ISR2 register) or according to the transfer mode of the syn-
chronous channels (WRDY and UNRE in the ISR2 register).
If the interrupt is generated by the CHIDx or FCHIDx bits, the interrupt remains active until a
read operation in the ISR1 register occurs.
If the interrupt is generated by the WRDY, UNRE, CMPMx or CMPUx bits, the interrupt remains
active until a read operation in the ISR2 register occurs.
A channel interrupt is enabled by setting the corresponding bit in the IER1 and IER2 registers. A
channel interrupt is disabled by setting the corresponding bit in the IDR1 and IDR2 registers.