Datasheet
991
32117D–AVR-01/12
AT32UC3C
33.6.5.2 Source Clock Selection Criteria
The large number of source clocks can make selection difficult. The relationship between the
value in the ”Channel Period Register” on page 1040 (CPRDx) and the ”Channel Duty Cycle
Register” on page 1038 (CDTYx) can help the user. The event number written in the Period Reg-
ister gives the PWM accuracy. The Duty-Cycle quantum cannot be lower than 1/CPRDx value.
The higher the value of CPRDx, the greater the PWM accuracy.
For example, if the user writes 15 (in decimal) in CPRDx, the user is able to write a value
between 1 up to 14 in CDTYx Register. The resulting duty-cycle quantum cannot be lower than
1/15 of the PWM period.
33.6.5.3 Changing the Duty-Cycle, the Period and the Dead-Times
It is possible to modulate the output waveform duty-cycle, period and dead-times.
To prevent unexpected output waveform, the user must use the ”Channel Duty Cycle Update
Register” on page 1039, the ”Channel Period Update Register” on page 1042 and the ”Channel
Dead Time Update Register” on page 1046 (CDTYUPDx, CPRDUPDx and DTUPDx) to change
waveform parameters while the channel is still enabled.
• If the channel is an asynchronous channel (SYNCx=0 in ”Sync Channels Mode Register” on
page 1006 (SCM)), these registers hold the new period, duty-cycle and dead-times values
until the end of the current PWM period and update the values for the next period.
• If the channel is a synchronous channel and update method 0 is selected (SYNCx=1 and
UPDM=0 in SCM register), these registers hold the new period, duty-cycle and dead-times
values until the UPDULOCK bit is written to one (in ”Sync Channels Update Control Register”
on page 1008 (SCUC)) and the end of the current PWM period, then update the values for
the next period.
• If the channel is a synchronous channel and update method 1 or 2 is selected (SYNCx=1 and
UPDM=1 or 2 in SCM register):
– these CPRDUPDx and DTUPDx registers hold the new period and dead-times
values until the UPDULOCK bit is written to one (in SCUC register) and the end of
the current PWM period, then update the values for the next period.
– the CDTYUPDx register holds the new duty-cycle value until the end of the update
period of synchronous channels (when UPRCNT is equal to UPR in ”Sync Channels
Update Period Register” on page 1009 (SCUP)) and the end of the current PWM
period, then updates the value for the next period
Note: If the update registers (CDTYUPDx, CPRDUPDx and DTUPDx) are written several times between
two updates, only the last written value is taken into account.
33.6.5.4 Changing the Synchronous Channels Update Period
It is possible to change the update period of synchronous channels (see Section 33.6.2.9 on
page 982 and Section 33.6.2.10 on page 984) while they are enabled.
To prevent an unexpected update of the synchronous channels registers, the user must use the
”Sync Channels Update Period Update Register” on page 1010 (SCUPUPD) to change the
update period of synchronous channels while they are still enabled. This register holds the new
value until the end of the update period of synchronous channels (when UPRCNT is equal to