Datasheet

989
32117D–AVR-01/12
AT32UC3C
33.6.4 PWM Event Lines
The PWM provides 2 independent event lines intended to trigger actions in other peripherals (in
particular for ADC (Analog to Digital Converter)).
A pulse (one cycle of the master clock (CLK_PWM))is generated on an event line, when at least
one of the selected comparisons is matching. The comparisons can be selected independently
by the CSEL bits in the ”Event Line x Register” on page 1026 (ELxMR for the Event Line x).
Figure 33-16. Event Line Block Diagram
PULSE
GENERATOR
Event Line x
CSEL0 (PWM_ELxMR)
CMPS0 (PWM_ISR2)
CSEL1 (PWM_ELxMR)
CMPS1 (PWM_ISR2)
CSEL2 (PWM_ELxMR)
CMPS2 (PWM_ISR2)
CSEL7 (PWM_ELxMR)
CMPS7 (PWM_ISR2)