Datasheet

988
32117D–AVR-01/12
AT32UC3C
The update of the comparison x configuration and the comparison x value is triggered periodi-
cally after the comparison x update period. It is defined by the CUPR field in the CMPxM. The
comparison unit has an update period counter independent from the period counter to trigger
this update. When the value of the comparison update period counter CUPRCNT (in CMPxM)
reaches the value defined by CUPR, the update is triggered. The comparison x update period
CUPR itself can be updated while the channel 0 is enabled by using the CMPxMUPD register.
CAUTION: to be taken into account, writing in the CMPxVUPD register must be followed by a
write in the CMPxMUPD register.
The comparison match and the comparison update can be a source of an interrupt, but only if it
is enabled and not masked. These interrupts can be enabled by the ”Interrupt Enable Register
2” on page 1011 and disabled by the ”Interrupt Disable Register 2” on page 1012. The compari-
son match interrupt and the comparison update interrupt are reset by reading the ”Interrupt
Status Register 2” on page 1014.
Figure 33-15. Comparison Waveform
CCNT0
CVUPD
0x6 0x2
CVMVUPD
CV
0x6
0x2
0x6
0x6
CVM
Comparison Update
CMPU
CTRUPD
0x1 0x2
CPR
0x1 0x3
0x0 0x1 0x0 0x1 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3
CPRCNT
0x0 0x1 0x2 0x3 0x0 0x1 0x2
0x0
0x1 0x2 0x0 0x1
CUPRCNT
CPRUPD
0x1 0x3
CUPRUPD
0x3 0x2
CTR
0x1 0x2
CUPR
0x3 0x2
Comparison Match
CMPM