Datasheet

985
32117D–AVR-01/12
AT32UC3C
Sequence for Method 3:
1. Select the automatic write of duty-cycle values and automatically update by setting the
UPDM field to 2 in the SCM register.
2. Define the synchronous channels by the SYNCx bits in the SCM register.
3. Define the update period by the UPR field in the SCUP register.
4. Define when the WRDY bit and the corresponding PDCA transfer request must be set
in the update period by the PTRM bit and the PTRCS field in the SCM register (at the
end of the update period or when a comparison matches).
5. Define the PDCA transfer settings for the duty-cycle values and enable it in the PDCA
registers
6. Enable the synchronous channels by writing CHID0 in the ENA register.
7. If an update of the period value and/or of the dead-time values is required, write regis-
ters that need to be updated (CPRDUPDx, DTUPDx), else go to Step 10.
8. Write UPDULOCK to one in SCUC.
9. The update of these registers will occur at the beginning of the next PWM period. At
this moment the UPDULOCK bit is reset, go to Step 7. for new values.
10. If an update of the update period value is required, check first that write of a new update
value is possible by polling the WRDY bit (or by waiting for the corresponding interrupt)
in the ISR2 register, else go to Step 13.
11. Write register that need to be updated (SCUPUPD).
12. The update of this registers will occur at the next PWM period of the synchronous chan-
nels when the Update Period is elapsed. Go to Step 10. for new values.
13. Check the end of the PDCA transfer with the Transfer Complete bit in the PDCA status
register. If the transfer is ended define a new PDCA transfer in the PDCA registers, for
new duty-cycle values. Go to Step 5.