Datasheet

984
32117D–AVR-01/12
AT32UC3C
33.6.2.10 Method 3: Automatic write of duty-cycle values and automatic trigger of the update
In this mode, the update of the duty cycle values is made automatically by the Peripheral DMA
Controller (PDCA). The update of the period value, the dead-time values and the update period
value must be made by writing in their respective update registers with the CPU (respectively
CPRDUPDx, DTUPDx and SCUPUPD).
To trigger the update of the period value and the dead-time values, the user must use the
UPDULOCK bit which allows to update synchronously (at the same PWM period) the synchro-
nous channels:
• If the UPDULOCK bit is set to 1, the update is done at the next PWM period of the
synchronous channels.
• If the UPDULOCK bit is not set to 1, the update is locked and cannot be performed.
After writing the UPDULOCK bit to one, it is held at this value until the update occurs, then it is
read 0.
The update of the duty-cycle values and the update period value is triggered automatically after
an update period.
To configure the automatic update, the user must define a value for the Update Period by the
UPR field in the ”Sync Channels Update Period Register” on page 1009 (SCUP). The PWM con-
troller waits UPR+1 periods of synchronous channels before updating automatically the duty
values and the update period value.
Using the PDCA removes processor overhead by reducing its intervention during the transfer.
This significantly reduces the number of clock cycles required for a data transfer, which
improves micro controller performance.
The PDCA must write the duty-cycle values in the synchronous channels index order. For exam-
ple if the channels 0, 1 and 3 are synchronous channels, the PDCA must write the duty-cycle of
the channel 0 first, then the duty-cycle of the channel 1, and finally the duty-cycle of the channel
3.
The following status are reported in the ”Interrupt Status Register 2” on page 1014 (ISR2):
• WRDY: this bit is set to 1 when the PWM Controller is ready to receive new duty-cycle values
and a new update period value. It is reset to 0 when the ISR2 register is read. The user can
choose to synchronize the WRDY bit and the PDCA transfer request with a comparison
match (see Section 33.6.3 on page 987), by the PTRM and PTRCS fields in the SCM
register.
• UNRE: this bit is set to 1 when the update period defined by the UPR field is elapsed while
the whole data has not been written by the PDCA. It is reset to 0 when the ISR2 register is
read.
Depending on the interrupt mask in the IMR2 register, an interrupt can be generated by these
bits.