Datasheet

982
32117D–AVR-01/12
AT32UC3C
33.6.2.9 Method 2: Manual write of duty-cycle values and automatic trigger of the update
In this mode, the update of the period value, the duty-cycle values, the dead-time values and the
update period value must be made by writing in their respective update registers with the CPU
(respectively CPRDUPDx, CDTYUPDx, DTUPDx and SCUPUPD).
To trigger the update of the period value and the dead-time values, the user must use the
UPDULOCK bit of the ”Sync Channels Update Control Register” on page 1008 (SCUC) which
allows to update synchronously (at the same PWM period) the synchronous channels:
• If the UPDULOCK bit is set to 1, the update is done at the next PWM period of the
synchronous channels.
• If the UPDULOCK bit is not set to 1, the update is locked and cannot be performed.
After writing the UPDULOCK bit to one, it is held at this value until the update occurs, then it is
read 0.
The update of the duty-cycle values and the update period is triggered automatically after an
update period.
To configure the automatic update, the user must define a value for the Update Period by the
UPR field in the ”Sync Channels Update Period Register” on page 1009 (SCUP). The PWM con-
troller waits UPR+1 periods of synchronous channels before updating automatically the duty
values and the update period value.
The status of the duty-cycle value write is reported in the ”Interrupt Status Register 2” on page
1014 (ISR2) by the following bits:
• WRDY: this bit is set to 1 when the PWM Controller is ready to receive new duty-cycle values
and a new update period value. It is reset to 0 when the ISR2 register is read.
Depending on the interrupt mask in the IMR2 register, an interrupt can be generated by these
bits.
Sequence for the Method 2:
1. Select the manual write of duty-cycle values and the automatic update by writing the
UPDM field to one in the SCM register
2. Define the synchronous channels by the SYNCx bits in the SCM register.
3. Define the update period by the UPR field in the SCUP register.
4. Enable the synchronous channels by writing CHID0 in the ENA register.
5. If an update of the period value and/or of the dead-time values is required, write regis-
ters that need to be updated (CPRDUPDx, DTUPDx), else go to Step 8.
6. Write UPDULOCK to one in SCUC.
7. The update of these registers will occur at the beginning of the next PWM period. At
this moment the UPDULOCK bit is reset, go to Step 5. for new values.
8. If an update of the duty-cycle values and/or the update period is required, check first
that write of new update values is possible by polling the WRDY bit (or by waiting for the
corresponding interrupt) in the ISR2 register.
9. Write registers that need to be updated (CDTYUPDx, SCUPUPD).
10. The update of these registers will occur at the next PWM period of the synchronous
channels when the Update Period is elapsed. Go to Step 8. for new values.