Datasheet

981
32117D–AVR-01/12
AT32UC3C
33.6.2.8 Method 1: Manual write of duty-cycle values and manual trigger of the update
In this mode, the update of the period value, the duty-cycle values and the dead-time values
must be made by writing in their respective update registers with the CPU (respectively CPR-
DUPDx, CDTYUPDx and DTUPDx).
To trigger the update, the user must use the UPDULOCK bit of the ”Sync Channels Update Con-
trol Register” on page 1008 (SCUC) which allows to update synchronously (at the same PWM
period) the synchronous channels:
• If the UPDULOCK bit is set to 1, the update is done at the next PWM period of the
synchronous channels.
• If the UPDULOCK bit is not set to 1, the update is locked and cannot be performed.
After writing the UPDULOCK bit to 1, it is held at this value until the update occurs, then it is read
0.
Sequence for the Method 1:
1. Select the manual write of duty-cycle values and the manual update by writing the
UPDM field to zero in the SCM register
2. Define the synchronous channels by the SYNCx bits in the SCM register.
3. Enable the synchronous channels by writing CHID0 in the ENA register.
4. If an update of the period value and/or the duty-cycle values and/or the dead-time val-
ues is required, write registers that need to be updated (CPRDUPDx, CDTYUPDx and
DTUPDx).
5. Write UPDULOCK to one in SCUC.
6. The update of the registers will occur at the beginning of the next PWM period. At this
time the UPDULOCK bit is reset, go to step 4) for new values.
Figure 33-10. Method 1 (UPDM=0)
CCNT0
CDTYUPD
0x20
0x40 0x60
UPDULOCK
CDTY
0x20
0x40 0x60