Datasheet

980
32117D–AVR-01/12
AT32UC3C
33.6.2.10 on page 984). The user can choose to synchronize the PDCA transfer request with
a comparison match (see Section 33.6.3 on page 987), by the PTRM and PTRCS fields in
the SCM register.
Table 33-2. Summary of the update of registers of Synchronous Channels
UPDM=0 UPDM=1 UPDM=2
Period Value
(CPRDUPDx)
Write by the CPU
Update is triggered at the
next PWM period as soon as
the UPDULOCK bit is set to 1
Dead-Time Values
(
DTUPDx)
Write by the CPU
Update is triggered at the
next PWM period as soon as
the UPDULOCK bit is set to 1
Duty-Cycle Values
(
CDTYUPDx)
Write by the CPU Write by the CPU Write by the PDCA
Update is triggered at the next
PWM period as soon as the
UPDULOCK bit is set to 1
Update is triggered at the next
PWM period as soon as the update period
counter has reached the value UPR
Update Period Value
(SCUPUPD)
Not applicable Write by the CPU
Not applicable
Update is triggered at the next
PWM period as soon as the update period
counter has reached the value UPR