Datasheet

979
32117D–AVR-01/12
AT32UC3C
33.6.2.7 Synchronous Channels
Some channels can be linked together as synchronous channels. They have the same source
clock, the same period, the same alignment and are started together. In this way, their counters
are synchronized together.
The synchronous channels are defined by the SYNCx bits in the ”Sync Channels Mode Regis-
ter” on page 1006 (SCM). Only one group of synchronous channels is allowed.
When a channel is defined as a synchronous channel, the channel 0 is automatically defined as
a synchronous channel too, because the channel 0 counter configuration is used by all the syn-
chronous channels.
If a channel x is defined as a synchronous channel, it uses the following configuration fields of
the channel 0 instead of its own:
• CPRE0 field in CMR0 register instead of CPREx field in CMRx register (same source clock)
• CPRD0 field in CMR0 register instead of CPRDx field in CMRx register (same period)
• CALG0 field in CMR0 register instead of CALGx field in CMRx register (same alignment)
Thus writing these fields of a synchronous channel has no effect on the output waveform of this
channel (except channel 0 of course).
Because counters of synchronous channels must start at the same time, they are all enabled
together by enabling the channel 0 (by the CHID0 bit in the ENA register). In the same way, they
are all disabled together by disabling the channel 0 (by the CHID0 bit in the DIS register). How-
ever, a synchronous channel x different from channel 0 can be enabled or disabled
independently from others (by the CHIDx bit in the ENA and DIS registers).
Defining a channel as a synchronous channel while it is an asynchronous channel (by writing the
SYNCx bit to one while it was at zero) is allowed only if the channel is disabled at this time
(CHIDx=0 in
SR register). In the same way, defining a channel as an asynchronous channel while
it is a synchronous channel (by writing the SYNCx bit to zero while it was at one) is allowed only
if the channel is disabled at this time.
The UPDM (Update Mode) field in the SCM register allow to select one of the three methods to
update the registers of the synchronous channels:
• Method 1 (UPDM=0): the period value, the duty-cycle values and the dead-time values must
be written by the CPU in their respective update registers (respectively CPRDUPDx,
CDTYUPDx and DTUPDx).The update is triggered at the next PWM period as soon as the
UPDULOCK bit in the ”Sync Channels Update Control Register” on page 1008 (SCUC) is set
to 1 (see Section 33.6.2.8 on page 981).
• Method 2 (UPDM=1): the period value, the duty-cycle values, the dead-time values and the
update period value must be written by the CPU in their respective update registers
(respectively CPRDUPDx, CDTYUPDx and DTUPD). The update of the period value and of
the dead-time values is triggered at the next PWM period as soon as the UPDULOCK bit in
the ”Sync Channels Update Control Register” on page 1008 (SCUC) is set to 1. The update
of the duty-cycle values and the update period value is triggered automatically after an
update period defined by the UPR field in the ”Sync Channels Update Period Register” on
page 1009 (SCUP) (see Section 33.6.2.9 on page 982).
• Method 3 (UPDM=2): same as Method 2 apart from the fact that the duty-cycle values of ALL
synchronous channels are written by the Peripheral DMA Controller (PDCA) (see Section