Datasheet

978
32117D–AVR-01/12
AT32UC3C
• To prevent an unexpected activation of the status FSy bit in the FSR register, the FMODy bit
can be written to one only if the FPOLy bit has been previously configured to its final value.
• To prevent an unexpected activation of the Fault Protection on the channel x, the FPEx[y] bit
can be written to one only if the FPOLy bit has been previously configured to its final value.
If a comparison unit is enabled (see Section 33.6.3 on page 987) and if a fault is triggered in the
channel 0, in this case the comparison cannot match.
As soon as the fault protection is triggered on a channel, an interrupt (different from the interrupt
generated at the end of the PWM period) can be generated but only if it is enabled and not
masked. The interrupt is reset by reading the interrupt status register, even if the fault which has
caused the trigger of the fault protection is kept active.