Datasheet

977
32117D–AVR-01/12
AT32UC3C
33.6.2.6 Fault Protection
5 inputs provide fault protection which can force any of the PWM output pair to a programmable
value. This mechanism has priority over output overriding.
Figure 33-9. Fault Protection
The polarity level of the faults inputs are configured by the FPOL field in the ”Fault Mode Regis-
ter” on page 1021 (FMR).
The fault inputs can be glitch filtered or not in function of the FFIL field in the FMR register.
When the filter is enabled, glitches on fault inputs with a width inferior to the PWM internal clock
(CCK) period are rejected.
A fault becomes active as soon as its corresponding fault input has a transition to the pro-
grammed polarity level. If the corresponding FMOD bit is written to zero in the FMR register, the
fault remains active as long as the fault input is at this polarity level. If the corresponding bit
FMOD is written to one, the fault remains active until the fault input is not at this polarity level
anymore AND until it is cleared by writing the corresponding FCLR bit in the ”Fault Clear Regis-
ter” on page 1023 (FSCR). By reading the ”Fault Status ReSister” on page 1022 (FSR), the user
can read the current level of the fault inputs thanks to the FIV field, and can know which fault is
currently active thanks to the FS field.
Each fault can be taken into account or not by the fault protection mechanism in each channel.
To be taken into account in the channel x, the fault y must be enabled by the FPEx[y] bit in the
“PWM Fault Protection Enable Registers” (FPE1). However the synchronous channels (see
Section 33.6.2.7 on page 979) don’t use their own fault enable bits, but those of the channel 0
(FPE0[y] bits).
The fault protection on a channel is triggered when this channel is enabled AND when any one
of the faults that are enabled for this channel is active. It can be triggered even if the PWM inter-
nal clock (CCK) is not running but only by a fault input that is not glitch filtered.
When the fault protection is triggered on a channel, the fault protection mechanism forces the
channel outputs to the values defined by the FPVHx and FPVLx fields in the ”Fault Protection
Value Register” on page 1024 (FPV) and leads to a reset of the counter of this channel. The out-
put forcing is made asynchronously to the channel counter.
CAUTION:
FIV0
fault input 0
Fault protection
on PWM
channel x
Glitch
Filter
FFIL0
from fault 0
from fault y
1
0
=
FPOL0 FMOD0
1
0
Fault 0 Status
FS0
FIV1
Glitch
Filter
FFIL1
1
0
=
FPOL1
SET
CLR
FMOD1
1
0
OUT
Fault 1 Status
FS1
fault input 1
from fault 1
1
0
0
1
From Output
Override
OOHx
OOLx
From Output
Override
FPVHx
FPVLx
PWMHx
PWMLx
fault input y
FMOD1
SET
CLR
Write FCLR0 at 1
OUT
FMOD0
Write FCLR1 at 1
SYNCx
1
0
FPEx[0]
FPE0[0]
SYNCx
1
0
FPEx[1]
FPE0[1]