Datasheet

970
32117D–AVR-01/12
AT32UC3C
33.6.2 PWM Channel
33.6.2.1 Block Diagram
Figure 33-3. Functional View of the Channel Block Diagram
Each of the 4 channels is composed of six blocks:
• A clock selector which selects one of the clocks provided by the clock generator (described in
Section 33.6.1 on page 968).
• A counter clocked by the output of the clock selector. This counter is incremented or
decremented according to the channel configuration and comparators matches. The size of
the counter is 20 bits.
• A comparator used to compute the OCx output waveform according to the counter value and
the configuration. The counter value can be the one of the channel counter or the one of the
channel 0 counter according to SYNCx bit in the ”Sync Channels Mode Register” on page
1006 (SCM).
• A 2-bit configurable gray counter enables the stepper motor driver. One gray counter drives 2
channels.
• A dead-time generator providing two complementary outputs (DTOHx/DTOLx) which allows
to drive external power control switches safely.
• An output override block that can force the two complementary outputs to a programmed
value (OOOHx/OOOLx).
• An asynchronous fault protection mechanism that has the highest priority to override the two
complementary outputs in case of fault detection (PWMHx/PWMLx).
counter
channel 0
Channel x
update
period
duty-
cycle
counter
channel x
comp
arator
MUX
clock
selector
PWMHx
PWMLx
dead-time
generator
output
override
fault
protection
DTOHx OOOHx
OOOLx
MUX
DTOLx
OCx
SYNCx
2-bit gray
counter z
z=0 (x=0, y=1)
z=1 (x=2, y=3)
z=2 (x=4, y=5)