Datasheet

969
32117D–AVR-01/12
AT32UC3C
The PWM internal clock (named CCK and driven either by CLK_PWM or by GCLK) is divided in
the clock generator module to provide different clocks available for all channels. Each channel
can independently select one of the divided clocks.
The selection of the source clock of the PWM counters is made by the CLKSEL bit in the CLK
Register. In asynchronous clocking mode (CLKSEL=1, GCLK selected), the PWM counters and
the prescaler allow running the CPU from any clock source while the prescaler is operating on a
faster clock (GCLK).
The clock generator is divided in three blocks:
– a modulo n counter which provides 11 clocks: F
CCK
, F
CCK
/2, F
CCK
/4, F
CCK
/8, F
CCK
/16,
F
CCK
/32, F
CCK
/64, F
CCK
/128, F
CCK
/256, F
CCK
/512, F
CCK
/1024
– two linear dividers (1, 1/2, 1/3,... 1/255) that provide two separate clocks: clkA and
clkB
Each linear divider can independently divide one of the clocks of the modulo n counter. The
selection of the clock to be divided is made according to the PREA (PREB) field of the PWM
Clock register (PWM_CLK). The resulting clock clkA (clkB) is the clock selected divided by DIVA
(DIVB) field value.
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) are set to 0. This implies
that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock “CCK”. This sit-
uation is also true when the PWM master clock is turned off through the Power Management
Controller.
CAUTION:
• Before using the PWM, the programmer must first enable the PWM clock in the Power
Manager (PM).
• The master clock frequency (CLK_PWM) must be lower than half of the generic clock
frequency (GCLK) due to the synchronization mechanism between both clock domains.
• After selecting a new PWM input clock (written CLKSEL to a new value), no write in any
PWM registers must be attempted before a delay of 2 master clock periods (CLK_PWM).
This is the time needed by the PWM to switch the source of the internal clock (CCK).