Datasheet

968
32117D–AVR-01/12
AT32UC3C
33.6 Functional Description
The PWM Controller is primarily composed of a clock generator module and 4 channels.
• The clock generator module provides 13 clocks. Its source clock is chosen according to the
CLKSEL bit in the Clock Register (CLK). It allows to select:
– CLK_PWM: the master clock (clock of the peripheral bus to which the PWM is
connected)
– GCLK: the generic clock (high frequency clock which is asynchronous to
CLK_PWM)
• Each channel can independently choose one of the clock generator outputs.
• Each channel generates an output waveform with attributes that can be defined
independently for each channel through the user interface registers.
33.6.1 PWM Clock Generator
Figure 33-2.
Functional View of the Clock Generator Block Diagram
modulo n counter
CCK
CLK_PWM
GCLK
CLKSEL
Divider
A
PREA DIVA
clkA
Divider
B
PREB DIVB
clkB
CCK
CCK/2
CCK/4
CCK/32
CCK/16
CCK/8
CCK/64
CCK/128
CCK/256
CCK/512
CCK/1024