Datasheet

965
32117D–AVR-01/12
AT32UC3C
33.3 Block Diagram
Figure 33-1. Pulse Width Modulation Controller Block Diagram
PWM
Channel x
update
period
duty-
cycle
counter
channel x
comp
arator
MUX
clock
selector
PWMH[x]
PWML[x]
I/O
controller
PWMH[0]
PWML[0]
Clock generator
CLK_PWM GCLK
EXT_
FAULTS[i]
EXT_
FAULTS[i]
Comparison
Units
Event
Generator
PEVC
event 0
event 1
User Interface
Peripheral Bus
PDCA
Channel 0
counter
channel 0
Channel y (=x+1)
update
period
duty-
cycle
counter
channel y
dead-time
generator
output
override
fault
protection
MUX
SYNCy
DTOHy OOOHy
OOOLy
clock
selector
comp
arator
2-bit gray
counter z
z=0 (x=0, y=1)
z=1 (x=2, y=3)
z=2 (x=4, y=5)
MUX
DTOLy
OCy
dead-time
generator
output
override
fault
protection
DTOHx OOOHx
OOOLx
MUX
DTOLx
OCx
SYNCx
PWMH[y]
PWML[y]