Datasheet

963
32117D–AVR-01/12
AT32UC3C
33. Pulse Width Modulation Controller (PWM)
Rev. 5.0.1.0
33.1 Features
• 4 channels
• Common clock generator providing thirteen different clocks
– A modulo n counter providing eleven clocks
– Two independent linear dividers working on modulo n counter outputs
– High frequency asynchronous clocking mode
• Independent channels
– Independent 20-bit counter for each channel
– Independent complementary outputs with 16-bit dead-time generator (also called dead-band
or non-overlapping time) for each channel
– Independent enable disable command for each channel
– Independent clock selection for each channel
– Independent period, duty-cycle and dead-time for each channel
– Independent double buffering of period, duty-cycle and dead-times for each channel
– Independent programmable selection of the output waveform polarity for each channel
– Independent programmable center or left aligned output waveform for each channel
– Independent output override for each channel
• 2 2-bit Gray up/down channels for stepper motor control
• Synchronous channel mode
– Synchronous channels share the same counter
– Mode to update the synchronous channels registers after a programmable number of periods
– Synchronous channels supports connection with peripheral DMA controller which offers
buffer transfer without processor intervention to update duty-cycle values
• 2 independent events lines intended to synchonize ADC conversions
• 8 comparison units intended to generate interrupts, pulses on event lines and PDC tranfer
requests
• 5 programmable fault inputs providing an asynchronous protection of PWM outputs
• Write-Protect registers
33.2 Overview
The PWM Controller (PWM) controls 4 channels independently. Each channel controls two com-
plementary square output waveforms. Characteristics of the output waveforms such as period,
duty-cycle, polarity and dead-times (also called dead-bands or non-overlapping times) are con-
figured through the user interface. Each channel selects and uses one of the clocks provided by
the clock generator. The clock generator provides several clocks resulting from the division of
the PWM internal clock (CCK). This internal clock can be driven either by the master clock
(CLK_PWM) or by the generic clock (GCLK).
All PWM accesses are made through registers mapped on the peripheral bus. All channels inte-
grate a double buffering system in order to prevent an unexpected output waveform while
modifying the period, the duty-cycle or the dead-times.
Channels can be linked together as synchronous channels to be able to update their duty-cycle
or dead-times at the same time.
The update of duty-cycles of synchronous channels can be performed by the Peripheral DMA
Controller Channel (PDCA) which offers buffer transfer without processor Intervention.