Datasheet

90
32117D–AVR-01/12
AT32UC3C
• BOD50DET - 5V Brown out detection:
– Set when a 0 to 1 transition on the PCLKSR.BOD50DET bit is detected.
• BOD33DET - 3.3V Brown out detection:
– Set when a 0 to 1 transition on the PCLKSR.BOD33DET bit is detected.
• BODDET - 1.8V Brown out detection:
– Set when a 0 to 1 transition on the PCLKSR.BODDET bit is detected.
• PLL1LOCK - PLL1 locked:
– Set when a 0 to 1 transition on the PCLKSR.PLL1LOCK bit is detected.
• PLL0LOCK - PLL0 locked:
– Set when an 0 to 1 transition on the PCLKSR.PLL0LOCK bit is detected.
• RCOSC8MRDY - 8MHz / 1MHz RCOSC Ready:
– Set when a 0 to 1 transition on the PCLKSR.RCOSC8MRDY bit is detected.
• OSC32RDY - 32KHz Oscillator Ready:
– Set when a 0 to 1 transition on the PCLKSR.OSC32RDY bit is detected.
• OSCR1DY - OSC1 Ready:
– Set when a 0 to 1 transition on the PCLKSR.OSC1RDY bit is detected.
• OSCR0DY - OSC0 Ready:
– Set when a 0 to 1 transition on the PCLKSR.OSC0RDY bit is detected.
This allows the user to allocate separate handlers and priorities to the different interrupt types.
The interrupt request will be generated if the corresponding bit in the Interrupt Mask Register
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable
Register (IDR). The interrupt request remains active until the corresponding bit in the Interrupt
Status Register (ISR) is cleared by writing a one to the corresponding bit in the Interrupt Clear
Register (ICR).