Datasheet

893
32117D–AVR-01/12
AT32UC3C
32.6.3 USB Host Operation
32.6.3.1 Host Enabling
Figure 32-16 on page 893 describes the USBC host mode main states.
Figure 32-16. Host mode states
After a hardware reset, the USBC host mode is in the Reset state (see Section 32.6.1.1).
When the USBC is enabled (USBCON.USBE = 1) in host mode (USBSTA.ID = 0) it enters Idle
state and waits for a device connection. Once a device is connected, the USBC enters the
Ready state, which does not require the USB clock to be activated.
In host mode the USBC will suspend the USB bus by not transmitting any Start Of Frame (SOF)
packets (the Start of Frame Generation Enable bit in the Host Global Interrupt register
UHCON.SOFE is zero). The USBC enters the Suspend state when the USB bus is suspended,
and exits when SOF generation is resumed.
32.6.3.2 Device detection
A device is detected by the USBC in host mode when DP or DM are not tied low, i.e., when a
device DP or DM pull-up resistor is connected. To enable this detection, the host controller has
to supply the device with VBUS power, which is done when USBSTA.VBUSRQ is one.
The device disconnection is detected by the host controller when both DP and DM are pulled
down.
32.6.3.3 Description of pipes
In host mode, the term “pipe” is used instead of “endpoint”. A host pipe corresponds to a device
endpoint, as illustrated by Figure 32-17 on page 894 from the USB specification.
Ready
Idle
Device
Disconnection
<any
other
state>
Device
Connection
Macro off
Clock stopped
Device
Disconnection
Suspend
SOFE = 1
SOFE = 0